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微晶硅薄膜晶体管稳定性研究

李 娟 吴春亚 赵淑云 刘建平 孟志国 熊绍珍 张 芳

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微晶硅薄膜晶体管稳定性研究

李 娟, 吴春亚, 赵淑云, 刘建平, 孟志国, 熊绍珍, 张 芳

Investigation on stability of microcrystalline silicon thin film transistors

Li Juan, Wu Chun-Ya, Zhao Shu-Yun, Liu Jian-Ping, Meng Zhi-Guo, Xiong Shao-Zhen, Zhang Fang
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  • 对有源区处于结构过渡区的微晶硅底栅薄膜晶体管,测试其偏压衰退特性时,观察到一种“自恢复”的衰退现象.当栅和源漏同时施加10 V的偏压时,测试其源-漏电流随时间的变化,发现源-漏电流先衰减、而后又开始恢复上升的反常现象.而当采用栅压为10 V、源-漏之间施加零偏压的模式时,源-漏电流随时间呈先是几乎指数式下降、随之是衰退速度减缓的正常衰退趋势.就此现象进行了初步探讨.
    Instability of a bottom gate microcrystalline silicon (μc-Si) thin film transistor (TFT), of which the active layer was deposited by very high frequency-plasma enhanced chemical vapor deposition with silane concentration of 4% diluted by H2, was measured and compared under two different gate bias stress conditions. A new instability phenomenon of TFT under the voltage bias stress of Vgs=Vds=10 V was found, where the ratio of the source-drain current of μc-Si TFT to its initial value decreases first, then stays flat for a period of time, then increases. However, under the voltage bias stress of Vgs=10 V(Vds=0 V), the source-drain current of μc-Si TFT decreases as normal exponential decay. Analysis on the change of sub-threshold swing S and threshold voltage Vth with stress time indicated the recoverable degradation could have resulted from the electron trapping and releasing in μc-Si TFT treated by gate-bias stress with Vds≠0.
    • 基金项目: 国家高技术研究发展计划(批准号:2004AA303570)、国家自然科学基金重点项目(批准号:60437030)、天津市自然科学基金(批准号:05YFJMJC01400)和教育部留学回国人员科研启动基金资助的课题.
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  • 文章访问数:  8028
  • PDF下载量:  1334
  • 被引次数: 0
出版历程
  • 收稿日期:  2005-12-28
  • 修回日期:  2006-08-21
  • 刊出日期:  2006-06-05

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