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双层结构突触仿生忆阻器的时空信息传递及稳定性

朱玮 刘兰 文常保 李杰

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双层结构突触仿生忆阻器的时空信息传递及稳定性

朱玮, 刘兰, 文常保, 李杰

Spatiotemporal signal processing and device stability based on bi-layer biomimetic memristor

Zhu Wei, Liu Lan, Wen Chang-Bao, Li Jie
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  • 现有计算机体系架构下的神经网络难以对多任务复杂数据进行高效处理, 成为制约人工智能技术发展的瓶颈之一, 而人脑的并行运算方式具有高效率、低功耗和存算一体的特点, 被视为打破传统冯·诺依曼计算体系最具潜力的运算体系. 突触仿生器件是指从硬件层面上实现人脑神经拟态的器件, 它可以模拟脑神经对信息的处理方式, 即“记忆”和“信息处理”过程在同一硬件上实现, 这对于构建新的运算体系具有重要的意义. 近年, 制备仿生突触器件的忆阻材料已获得进展, 但多聚焦于神经突触功能的模拟, 对于时空信息感知和传递的关键研究较为缺乏. 本文通过制备一种双层结构忆阻器, 实现了突触仿生器件的基本功能包括双脉冲易化和抑制、脉冲时间依赖突触可塑性(spiking time dependent plasticity, STDP)和经验式学习等, 还对器件的信息感知、传递特性和稳定性进行了研究, 发现该器件脉冲测试结果满足神经网络处理时空信息的基本要求, 这一结果可以为忆阻器在类脑芯片中的应用提供参考.
    The neural network under the current computer architecture is difficult to process complex data efficiently, thus becoming one of the bottlenecks restricting the development of artificial intelligence technology. The human brain has the characteristics of high efficiency, low power consumption and integration of memory and computing, and is regarded as a most potential computing system to break the traditional von Neumann computing system. Synaptic biomimetic device is to realize the neural mimicry of human brain from the hardware level. It can simulate the information processing mode of brain nerve, that is, the process of “memory” and “calculation” can be realized on the same device, which is of great significance in building a new computing system. In recent years, the fabrication of memristor materials for bio-mimetic synaptic devices has made progress, but most of them focus on the simulation of synaptic function. The key research of pulse signal perception and information transmission is relatively lacking. In this paper, an bi-layer memristor with structure Al/nc-Al AlN/A2O3/Ag is fabricated by rf sputtering method to realize the basic functions of bionic synaptic devices. It is found that this bio-mimetic memristor exhibits bipolar switching property which is the basic condition to produce memristor based neural synapse. Both of PPF and PPD process can be observed and there will be no firing signal observed if the pulse interval is as large as 350 ms. The change of device conductance should be related to pulse voltage, frequency and pulse number applied. The larger pulse voltage, frequency and number will cause device conductance to increase sharply in both positive and negative pulse voltage region. The STDP measurement is executed with different sequence pulses from post and previous neuron separately. If the pulse of previous synapse comes in front of pulse from post synapse, the conductance will increase, which is so-called LTP process. If the pulse of previous neuron comes behind of pulse from post neuron, the conductance will be reduced as well. Triplet STDP measurement is executed with at least three pulses from previous and post neuron at the meanwhile. It is concluded that if the interval time of the first two pulses is fixed, the device conductance more depends on the value of the second and third pulse interval. Ebbinghaus forgetting curve can be used to explain the reason why the device conductance declines with time going by. The stability study of this memristor includes endurance and retention properties at both room and high temperature. It is found this biomimetic memristor can maintain its conductance for over 115.7 days at 85 ℃, which is long enough for current neural network design.
      通信作者: 朱玮, wzhu@chd.edu.cn
    • 基金项目: 国家自然科学青年科学基金(批准号: 61704010)和陕西省自然科学基金(批准号: 2020JM-238)资助的课题.
      Corresponding author: Zhu Wei, wzhu@chd.edu.cn
    • Funds: Project supported by the Young Scientists Fund of the National Natural Science Foundation of China (Grant No. 61704010) and the Natural Science Foundation of Shaanxi Province, China (Grant No. 2020JM-238).
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  • 图 1  (a) 器件TEM图; (b) 器件结构图; (c) 神经突触工作原理; (d) 连续100次正向电压扫描测试; (e) 连续100次负向电压扫描测试

    Fig. 1.  (a) TEM result of bi-layer memristor; (b) structure of memristor; (c) mechanisms of synapse working; (d) continued positive I-V biasing with 100 times; (e) continued negative I-V biasing with another 100 times.

    图 2  器件内EPSC和IPSC的脉冲测 (a) 施加单个正向脉冲的EPSC; (b) 双脉冲易化的EPSC; (c) 施加双正向脉冲但间隔时间350 ms的EPSC; (d) 施加单个负向脉冲的IPSC; (e) 双脉冲抑制的IPSC; (f) 施加双负向脉冲但间隔时间350 ms的IPSC

    Fig. 2.  Pulse voltage measurement of memristor: (a) EPSC with single positive pulse applied; (b) EPSC of PPF; (c) two positive pulses applied with 350 ms interval; (d) EPSC with single negative pulse applied; (e) IPSC of PPD; (f) two negative pulses applied with 350 ms interval.

    图 3  (a) 以100 Hz频率施加幅值和宽度为2 V和5 ms的正向脉冲, 器件权值随时间增加; (b) 以100 Hz频率施加幅值和宽度为–2 V和5 ms的负向脉冲, 器件权值随时间减小; (c) 以2 Hz频率施加幅值和宽度为2 V和5 ms的正向脉冲, 器件权值也会随时间减小

    Fig. 3.  (a) Device conductance increased with 100 Hz, 2 V in amplitude and 5 ms in width positive voltage pulse applied; (b) device conductance decreased with 100 Hz, -2 V in amplitude and 5 ms in width positive voltage pulse applied; (c) device conductance will decrease with 2 Hz, 2 V in amplitude and 5 ms in width positive voltage pulse applied.

    图 4  (a) 器件权值与施加脉冲数量和脉冲间隔的关系; (b) 器件达到最大权值所需脉冲数量与脉冲电压和间隔的关系; (c) STDP特性

    Fig. 4.  (a) The relationship of device conductance with pulse number and interval; (b) the pulse number needed to make device conductance maximized with different pulse voltage and interval; (c) STDP.

    图 5  (a) 后-前-后和前-后-前时序的神经元信号; (b) 三脉冲STDP器件权值的变化

    Fig. 5.  (a) Singal with post-pre-post and pre-post-pre sequence; (b) triplet-STDP.

    图 6  分别施加10个(a), 50个(b), 100个(c)和200个(d) 幅值为1.2 V、宽度为5 ms的脉冲电压后器件权值随时间减弱的特性

    Fig. 6.  The device conductance changed with time after applied (a) 10, (b) 50, (c) 100 and (d) 200 positive voltage pulses with the amplitude of 1.2 V and pulse width of 5 ms.

    图 7  (a) 器件最终权值与施加脉冲数量的关系; (b) 器件弛豫时间与施加脉冲数量的关系; (c) 器件弛豫时间与施加脉冲电压的关系

    Fig. 7.  (a) The relationship between device conductance and applied pulse number; (b) the relationship between device relaxation time and applied pulse number; (c) the relationship between device relaxation time and applied pulse voltage.

    图 8  (a) 循环测试; (b) 耐久测试; (c) 175, 200, 225和250 ℃高温测试

    Fig. 8.  (a) Duration study; (b) retention study at room and 50 ℃ temperature; (c) device failure time at high temperature 175, 200, 225 and 250 ℃.

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    Krestinskaya O, Salama K N, James A P 2020 Adv. Intell. Syst. 2 2000075Google Scholar

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    Shastri B J, Tait A N, Ferreira L T, Pernice W H P, Bhaskaran H, Wright C D, Prucnal P R 2021 Nat. Photonics 15 102Google Scholar

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    Lim D H, Wu S, Zhao R, Lee J H, Jeong H, Shi L 2021 Nat. Commun. 12 319Google Scholar

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出版历程
  • 收稿日期:  2021-02-05
  • 修回日期:  2021-03-02
  • 上网日期:  2021-08-25
  • 刊出日期:  2021-09-05

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