基于3D-NAND的神经形态计算

陈阳洋; 何毓辉; 缪向水; 杨道虹

doi:10.7498/aps.71.20220974

摘要

神经形态芯片是一种新兴的AI芯片. 神经形态芯片基于非冯·诺依曼架构, 模拟人脑的结构和工作方式, 相比冯·诺依曼架构的AI芯片, 神经形态芯片在效率和能耗上有显著的优势. 3D-NAND闪存工艺成熟并且存储密度极高, 基于3D-NAND的神经形态芯片受到许多研究者的关注. 然而由于该技术的专利性质, 少有基于3D-NAND神经形态计算的硬件实现. 本文综述了用3D-NAND实现神经形态计算的工作, 介绍了其中前向传播和反向传播的机制, 并提出了目前3D NAND在器件、结构和架构上需要的改进以适用于未来的神经形态计算.

关键词:

Abstract

A neuromorphic chip is an emerging AI chip. The neuromorphic chip is based on non-Von Neumann architecture, and it simulates the structure and working principle of the human brain. Compared with non-Von Neumann architecture AI chips, the neuromorphic chips have significant improvement of efficiency and energy consumption advantages. The 3D-NAND flash memory has the merits of a mature process and ultra-high storage density, and recently it attracted many researchers’ attention. However, owing to the proprietary nature of the technology, there are few hardware implementations. This paper reviews the present research status of neuromorphic computing by using the 3D-NAND flash memory, introduces the forward propagation and backward propagation schemes, and proposes several improvements on the device, structure, and architecture of 3D NAND for neuromorphic computing.

Keywords:

作者及机构信息

1.
华中科技大学, 博士后流动站, 武汉　430074

2.
武汉新芯集成电路制造有限公司, 博士后工作站, 武汉　430205

3.
江城实验室, 武汉　430205

4.
华中科技大学集成电路学院, 武汉　430074

通信作者: 杨道虹, alan_yang@xmcwh.com

Authors and contacts

1.
Post-doctoral Mobile Station, Huazhong University of Science and Technology, Wuhan 430074, China

2.
Post-doctoral Work Station, Wuhan Xinxin Semiconductor Manufacturing Co., Ltd., Wuhan 430205, China

3.
Hubei Yangtze Memory Laboratories, Wuhan 430205, China

4.
School of Integrated Circuit, Huazhong University of Science and Technology, Wuhan 430074, China

Corresponding author: Yang Dao-Hong, alan_yang@xmcwh.com

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施引文献

图 1 AI模型训练的算力需求和单芯片运算性能^[1]

Fig. 1. Total amount of computing in AI training and single-core chip performance^[1].

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图 2 限制芯片性能提升的冯·诺依曼瓶颈^[2-4]

Fig. 2. The von Neumann bottleneck limits chip performance promotion^[2-4].

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图 3 神经形态计算的原理与芯片架构^[6]

Fig. 3. Neuromorphic computing architectures and paradigms^[6].

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图 4 基于非易失存储器的神经形态计算硬件方案^[7]　(a) 几种作为突触的非易失性存储器件, 其中包括PCM, ReRAM, STT-MRAM, FeRAM和FeFET; (b) 突触和神经元构成crossbar阵列结构用于神经形态计算; (c) 神经形态计算芯片的架构

Fig. 4. Use of non-volatile memory devices as synaptic storage^[7]: (a) Non-volatile memory cell as artificial synapse including PCM, ReRAM, STT-MRAM, FeRAM, and FeFET; (b) the implementation of neuromorphic computation on crossbar array consists of artificial synapses and neurons; (c) typical architecture of the neuromorphic chip.

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图 5 各种存储器的性能参数对比(数据来源于表 1)

Fig. 5. Performance comparison of various memories (data was extracted from Table 1 and plotted into a radar diagram).

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图 6 NOR和NAND的电路结构

Fig. 6. Circuit structure diagram of NOR flash and NAND flash.

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图 7 各种3D-NAND的技术方案^[40]

Fig. 7. A summary of 3D-NAND technologies^[40].

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图 8 (a) 栅极堆叠的TCAT技术^[41]; (b) 沟道堆叠的VG-NAND技术^[42]

Fig. 8. (a) TCAT technology with gate stack architecture^[41]; (b) VG-NAND technology with channel stack architecture^[42].

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图 9 (a) CTL单元的结构示意图(以栅极堆叠结构为例)^[43]; (b) 采用ISPP机制调控3D-NAND中CTL器件的阈值电压^[44]; (c) 3D-NAND中CTL器件的模拟电导特性, 即模拟权重调制特性^[45]

Fig. 9. (a) Illustration of typical gate-stack type 3D-NAND^[43]; (b) ISPP modulation of threshold voltage in CTL device^[44]; (c) analog conductivity characteristics of CTL devices in 3D-NAND^[45].

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图 10 (a) 基于NAND的神经形态计算法则^[46]; (b), (c) 前向传播和反向传播过程中NAND的操作方法^[45]

Fig. 10. (a) Learning rule of software-based and NAND-based neural network^[46]; 2D-NAND operation method in (b) forward and (c) backward propagation^[45].

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图 11 一种基于3D-NAND的VMM方案^[47]　(a) 3D-NAND的电路结构和VMM的操作方法; (b) 用于3D-NAND层间选通的外围电路结构

Fig. 11. A case of using 3D-NAND for VMM operation^[47]: (a) Circuit diagram and bias scheme of 3D-NAND array architecture for VMM; (b) peripheral circuitry for layer-to-layer selection.

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图 12 基于2D NAND的二值神经网络BNN^[48]　(a) 相邻的两个CTL器件组成差分对形式的突触, 与输入的信号进行同或运算(XNOR); (b), (c) BNN前向传播中NAND的操作方法以及NAND电路示意图; (d) 采用二值全连接神经网络和二值卷积神经网络分别用于MNIST和CIFAR-10图像库的识别性能

Fig. 12. A synaptic architecture based on 2D NAND for binary neural network (BNN) ^[48]: (a) NAND string structure for XNOR operation, in which two neighboring CTL device constructs a differential pair as one synapse; (b) operation scheme for forward propagation; (c) schematic diagram of synaptic array architecture; (d) the performance of binarized multi-layer and convolutional neural networks for MNIST and CIFAR-10 database recognition task respectively.

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图 13 采用SLC 3D-NAND实现4 bit精度的卷积神经网络方案^[49]　(a) 卷积神经网络的工作原理示意图(上), 涉及大量的MAC过程(下); (b) 对于多bit权重的MAC过程, 用多个SLC器件构成一个多bit权重; (c) 4 bit精度输入与4 bit精度权重的MAC原理; (d) 卷积核电路的工作原理; (e) VGG 16神经网络的结构图以及用所设计的3D-NAND加速VGG 16的性能

Fig. 13. A case of SLC 3D-NAND for convolution neural network (CNN) with 4-bit resolution^[49]: (a) Flow schematic of CNN; (b) in a MAC array, plural SSLs to stand for multi-bit weight; (c) the arithmetic principle of MAC with 4-bit input and 4-bit weight (4I4W); (d) convolutional core circuit and working principle diagram; (e) schematic diagram of VGG 16 CNN and the simulated performance of 3D-NAND hardware implementation.

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图 14 基于MLC 3D-NAND的8-bit精度卷积方案^[50,51]　(a) 基于BiCS结构的3D-NAND电路图^[51]; (b) 权重的映射方式, 正、负权重存储在相邻的两个block中^[51]; (c) 2个8 bit精度的输入信号和2个8 bit精度的权重的乘加运算过程^[51]; (d) 基于eNAND的卷积核电路, 有7个block, 28个输入端口, 满足5 × 5卷积核的功能^[51]; (e) 卷积过程的信号时序图^[51]

Fig. 14. A case of MLC 3D-NAND for CNN with 8-bit resolution^[50,51]: (a) Circuit diagram of BiCS type 3D-NAND, the 3D structure can be flattened into a 2D structure^[51]; (b) weight mapping method, positive and negative weight stored in two neighboring blocks^[51]; (c) MAC operation principle of 2 inputs and two weights with 8-bit resolution^[51]; (d) convolutional core circuit diagram with 7 blocks and 28 input ports can be used for 5 × 5 convolution operation^[51]; (e) timing diagram of 5 × 5 convolution operation with 8-bit data and 8-bit weights^[51].

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图 15 基于3D NAND的S-Flash芯片用于卷积神经网络加速^[52]　(a) 卷积过程示意图; (b) MAC算子的比特对乘、加运算延迟时间的影响(左)和MAC算子的比特对累加运算延迟时间的影响(右); (c) S-Flash芯片的架构; (d) S-Flash中权重分布的示意图, 用16个SLC构成一个差分结构的突触; (e) 通过Booth编码分配权重; (f), (g) 同时操作的SSL和BL增大1倍, MAC次数缩减了1/4

Fig. 15. 3D NAND-based CNN accelerator named as S-Flash^[52]: (a) Convolutional operation of CNN; (b) normalized latency for multiplication, accumulation (left) and MAC operation in various multiplication units (right); (c) overall S-FLASH architecture; (d) overall weight data layout, in which a differential synapse constructed with 16 SLC; (e) weight allocation by Booth coding; (f), (g) double the concurrently operated BLs and SSLs, 4 times faster the MAC operation speed.

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图 16 S-Flash电路仿真的结果^[52]　(a) S-Flash/S-Flash^*/S-Flash^**运行VGG-16卷积神经网络时的能效; (b) S-Flash^**电路模块的面积对比和运行VGG-16时各电路模块的能耗对比; (c) S-Flash^**与其他芯片的性能参数对比

Fig. 16. Simulation result of S-Flash^[52]: (a) Energy efficiency evaluation result of each VGG-16 layer accelerated by S-Flash/S-Flash^*/S-Flash^**; (b) area and energy breakdown of S-FLASH^**; (c) comparison with the other platform.

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图 17 输入信号采用十进制编码的3D NAND芯片用于卷积神经网络加速^[53]　(a) 用3D NAND做VMM的操作方法; (b) 卷积核映射的方案; (c) subarray的结构示意图; (d) 芯片的架构示意图; (e) 用3D NAND芯片运行VGG-8神经网络用于CIFAR-10图片库识别时, 各电路模块的能耗对比; (f) 3D NAND与其他芯片的性能对比

Fig. 17. A 3D NAND CNN accelerator with decimal input coding^[53] (a) VMM operation method by using 3D NAND; (b) the mapping method of a CNN kernel; (c) designed subarray configuration; (d) hierarchy of the 3D NAND-based neuromorphic chip architecture; (e) energy breakdown of 3D NAND-based chip on VGG-8 network for the CIFAR-10 dataset; (f) comparison with other chips

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图 18 基于3D NAND的WTA神经网络用于非监督学习^[54]　(a) 具有差分对结构的3D NAND; (b) CTL器件的模拟权重调制特性; (c) 用3D NAND训练WTA神经网络的过程; (d) WTA神经网络的训练结果

Fig. 18. A 3D NAND-based WTA neural network for unsupervised learning^[54]: (a) Schematic of the differential pair in 3D NAND flash array; (b) analog weight modulation of measured CTL device; (c) the training procedure of WTA neural network using 3D NAND array; (d) stylized letter clustering results before and after training.

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图 19 3D-NAND中采用脉宽编码实现前向传播^[55]　(a) 前向传播的操作方式、神经网络示意图和WL上读电压的时序图; (b) 左: 前向传播的工作原理示示意图, 即两个标记为正、负权重的突触对构成一个突触, 输出电流相减后通过电容积分转化为电压V_c; 右: 读电压V_read、SSL上输入脉冲V_SSL和V_c的时序图; (c) 3层全连接CNN网络在权重精度为4 bit(QNN)和1 bit(BNN)条件下对CIFAR-10图片数据库的识别性能

Fig. 19. Forward propagation using 3D-NAND with pulse width modulation (PWM) scheme^[55]: (a) Operation scheme of forward propagation, schematic diagram of neural networks, the timing diagram of pulses applied to WLs; (b) Left: schematic diagram of synaptic string array consisting of synapses with positive weight (G⁺) and synapses with negative weight (G^–); Right: timing diagram of V_read, V_SSL, and V_c; (c) simulated classification accuracy of 4-bit QNN and BNN for CIFAR-10 images.

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图 20 差分对突触阵列中将正、负权重分开放置可实现反向传播^[56]　(a) 前向传播和反向传播过程中对应的突触阵列, 从矩阵运算角度上看互为转置结构; (b) 通常情况下, 差分对结构中的正、负权重在同一个阵列中, 突触阵列与前向传播过程中并非转置的关系, 无法实现反向传播功能; (c) 将正、负权重分开置于不同的阵列中, 可以实现反向传播过程

Fig. 20. Backward propagation can be implemented using a differential synaptic array where positive and negative weights are separated^[56]: (a) The matrix of synapse weight in forward and backward propagation are transposed; (b) synaptic array architecture consisting of two adjacent cells representing G⁺ and G^–, the weights cannot be transposed; (c) synaptic array architecture where G⁺ and G^– weights are separated in different arrays.

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图 21 基于3D-NAND的前向传播和反向传播的工作原理^[56]　(a) 前向传播中3D-NAND的操作方法; (b) 反向传播中3D-NAND的操作方法; (c) 具有n层全连接突触的神经网络结构; (d) 前向传播和反向传播中WL上选通电压V_read和导通电压V_pass的时序

Fig. 21. Forward and backward propagation using 3D-NAND with PWM scheme^[56]: (a) Synaptic array architecture based on NAND flash memory for forwarding propagation operation; (b) synaptic array architecture based on NAND flash memory for backward propagation operation; (c) schematic of neural networks consisting of n weight layers; (d) timing diagram of V_read and V_pass in forwarding propagation and backward propagation.

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图 22 器件特性和神经网络性能^[56]　(a) 器件的I_BL-V_BL特性随写入脉冲数量的变化; (b) 图(a)中器件的归一化电导随写脉冲数量的变化; (c) 导通电压V_pass和写电压V_PGM对阈值电压的影响; (d) 初始状态的器件和经历过擦写循环的器件对写入脉冲的响应; (e) 三层全连接神经网络的识别率; (f) 隐藏层数量对识别率的影响

Fig. 22. Device characteristics and neural network performance^[56]: (a) I_BL-V_BL curves with an increasing number of program pulses; (b) normalized conductance responses measured in (a); (c) I_BL-V_WL curves measured in a fresh, V_pass disturbed, and programmed cell; (d) conductance response of fresh and cycled cell; (e) recognition accuracy of 3-layer neural network; (f) recognition accuracy with the number of hidden layers.

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表 1 几种非易失性存储器的性能参数

Table 1. Benchmark table of performance of emerging memories and typical memories.

	新型存储器					主流存储器
	PCM	ReRAM	STT-MRAM	FeRAM	FeFET	NOR flash	NAND flash
器件结构	1T-1R	1T-1R	1T-1R	1T-1C/ 1T-1FTJ	1T	1T	1T
器件面积F ²	4—40	6—26	9—75	30—40	10—30	10	4
工艺节点/nm	14^[8,9]	14^[10]	22^[11]	130^[12]	22^[13]	40	15(2D) 80(3D)^[14]
芯片容量	16—64 GB (Intel optane)	1 MB— 32 GB^[10,15]	16 kB— 4 GB^[16,17]	16 kB— 128 MB^[18,19]	64 kB— 32 MB^[13,20]	1 MB—2 GB (Micron/Infineon/Macro- nix product manuals)	1 TB^[21]
写电压/V	< 3	< 1	< 2	< 3	～1.5	10—15	15—25
写时间/ns	75^[9]	1—10^[22]	3—14^[23,24]	1—10^[25]	1—10^[25]	10000^[26]	100000^[27]
写功耗/(pJ·bit^–1)	1^[28]	～10^[29]	4.5^[30]	0.1^[25]	1—10 fJ^[25]	49^[26]	～1000^[31]
读时间	12—130 ns^[8,32]	2.9—21 ns^[33,34]	2—26 ns^[30,35]	1—25 ns	1—10 ns	11 ns	3 μs^[27]
读功耗/(pJ·bit^–1)	2.47^[36]	1.76^[29]	0.7^[30]	9.8—19.2^[37]	0.27 fJ/bit^[38]	2.2^[26]	～100^[31]
开关比	> 10⁴	> 10³	> 2	> 2	> 10⁸	> 10⁸	> 10⁸
擦写次数	> 10^{10 [22]}	> 10¹²	> 10¹²	> 10¹²	10⁵—10⁹	< 10⁶	< 10⁵
保持时间/a	> 10	> 10	> 10	> 10	> 10	> 10	> 10
存储比特	2	6^[39]	1	3—4^[39]	2—3	2	4

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表 2 基于3 D-NAND的神经形态计算的各项工作比对

Table 2. A comparison of reviewed works.

	文献工作
	[45]	[47]	[48]	[49]	[50]	[52]	[53]	[54]	[55]	[56]
技术节点	N.A.	N.A.	N.A.	N.A.	65 nm	N.A.	32 nm	N.A.	26 nm	26 nm
芯片容量	N.A.	N.A.	N.A.	64 GB	N.A.	N.A.	1.13 GB	N.A.	N.A.	N.A.
器件类型	N.A.	SLC	SLC	SLC	SLC	SLC	SLC	Analog	MLC	PLC
输入端口	位线	字线	漏端选通管的字线	位线	漏端选通管的字线	位线	位线	字线	位线	位线
输入编码	脉冲幅值	N.A.	二值编码	数字编码	数字编码	数字编码	数字编码	二值编码	脉宽编码	脉宽编码
输入信号精度	模拟	N.A.	1 bit	4 bit	8 bit	8 bit	8 bit	1 bit	模拟	模拟
突触精度	N.A.	1 bit	1 bit	4 bit	8 bit	8 bit	8 bit	N.A.	4 bit/2 bit	6 bit
反向传播方式	另选转置的突触阵列, 误差信号在位线上输入	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A	N.A.	误差信号施加在源极选通管位线上
神经网络	3层全连接网络	N.A.	4层全连网络、 6层卷积 + 3层全连接	VGG16	LeNet-5	VGG-16	VGG-8	两层全连接网络	6层卷积 + 3层全连接	2—7层全连接网络
神经网络的突触数量	0.3 MB	N.A.	N.A.	138 MB	N.A.	N.A.	110 MB	27	N.A.	N.A.
数据集	MNIST	N.A.	MNIST, CIFAR-10	CIFAR-10	MNIST	N.A.	CIFAR-10	ZVN	CIFAR-10	MNIST
识别率	94.5%	N.A.	98.12%, 87.11%	90%	98.5%	N.A.	N.A.	N.A.	89.38% (4 bit 权重)、87.1% (2 bit权重)	95.65%
能效/ (TOPS·W^–1)	N.A.	N.A.	N.A.	～40	N.A.	0.3	12.95	N.A	N.A.	N.A.

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