Research progress of single event effect and reinforcement technology of SiC power metal-oxide-semiconductor field-effect transistors

QIU Yiwu; LIANG Di; YIN Yanan; DONG Lei; WANG Tao; ZHOU Xinjie

doi:10.7498/aps.74.20250273

Abstract

In extreme radiation environments, such as space nuclear reactor systems, deep-space probe power modules, and launch vehicle propulsion systems, high-voltage and high-power devices demonstrate significant practical value. Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) possess advantages including high breakdown voltage, thermal stability, and low on-state resistance, enabling further improvements in aerospace power supply efficiency. Therefore, research on radiation effects and radiation-hardening techniques for SiC power MOSFETs has rapidly emerged as a critical focus in the industry. Firstly, this paper reviews the developmental evolution of SiC power MOSFETs, analyzes the necessity of transitioning from planar gate to trench-gate architectures, and provides future prospects for advanced SiC power MOSFET technologies. Secondly, it systematically compiles current research achievements in single event burnout (SEB) and single event gate rupture (SEGR) caused by heavy ion irradiation in SiC power MOSFETs. Finally, based on a mechanistic analysis of radiation-induced single event damage in SiC power MOSFETs, this study summarizes recent progress of radiation-hardening technologies, aiming to provide valuable ideas for understanding radiation induced failure mechanisms and enhancing the radiation tolerance of SiC power MOSFETs.

Keywords:

Authors and contacts

1.
No.58 Research Institute, China Electronics Technology Group Corporation, Wuxi 214035, China
2.
Key Laboratory of Aerospace Integrated Circuits and Microsystem, Ministry of Industry and Information Technology, Nanjing 211106, China

Corresponding author: ZHOU Xinjie, zhouxinjie2000@sina.com

Funds: Project supported by the Innovation Fund for the Center for Technology Innovation for Anti-Radiation Applications, China (Grant No. KFZC2021010202).

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References

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图 1 SiC功率MOSFET器件结构示意图　(a)平面型MOSFET; (b)沟槽型MOSFET

Figure 1. Structure diagram of SiC power MOSFET device (not to scale): (a) VDMOSFET; (b) TGMOSFET.

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图 2 SiC功率MOSFET产品技术演变示意图

Figure 2. Technical evolution diagram of SiC power MOSFET products.

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图 3 几种沟槽型SiC MOSFET栅氧屏蔽结构示意图　(a) ROHM双沟槽结构^[15]; (b) Infineon非对称沟槽结构^[17]; (c)直接屏蔽结构^[29]; (d)间接屏蔽结构^[32]; (e)台阶沟槽结构^[33]; (f) P+埋层V型沟槽结构^[35]

Figure 3. Schematic diagrams of several trench-type SiC MOSFET gate oxide shielding structures (not to scale): (a) ROHM’s double-trench structure^[15]; (b) Infineon’s asymmetric trench structure^[17]; (c) direct shielding structure^[29]; (d) indirect shielding structure^[32]; (e) stepped trench structure^[33]; (f) P+ buried layer V-shaped trench structure^[35].

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图 4 功率MOSFET器件总剂量效应、位移损伤效应和单粒子效应损伤机理示意图

Figure 4. Damage mechanism diagram of power MOSFET’s total ionization dose, displacement damage and single event effect.

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图 5 重离子辐照过程中SiC MOSFET SEB过程与V_DS的关系^[44]

Figure 5. The SEB processing for SiC power MOSFET as a function of the drain-source bias V_DS during the heavy ion irradiation^[44].

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图 6 Ar, Fe, Kr和Xe离子辐照实验结果^[46]　(a)器件在V_DS = 60 V下Xe离子辐照时的I_D-V_GS和I_G-V_GS特性曲线; (b)辐照后V_DS扫描测试, 所有器件在580 V < V_DS < 700 V范围内失效. 原始状态下的I_D和I_G以灰色显示

Figure 6. Results from irradiations with Ar, Fe, Kr and Xe ions^[46]: (a) I_D-V_GS and I_G-V_GS of device exposed to Xe at V_DS = 60 V; (b) post-irradiation V_DS sweep; all the devices failed at 580 V < V_DS < 700 V. The pristine I_D and I_G are shown in gray.

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图 7 重离子入射　(a) 1 ps, (b) 10 ps, (c) 100 ps和(d) 1 ns后器件内部晶格温度分布图^[63]

Figure 7. Distribution of lattice temperature in device after heavy ion incident of (a) 1 ps, (b) 10 ps, (c) 100 ps, and (d) 1 ns^[63].

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图 8 (a) 在LET = 0.1 pC/μm, V_DS = 400 V条件下, 无N+源和有N+源器件在30, 100 ps和1 ns时离子撞击后的电子电流密度分布^[75]; (b) 垂直N沟道双扩散功率MOSFET辐射下的一维电场和载流子分布^[76]

Figure 8. (a) Electron current density distribution at 30, 100 ps, and 1 ns after the ion strike for device without N+ source and with N+ source (LET = 0.1 pC/μm, V_DS = 400 V)^[75]; (b) vertical N-channel double-diffused power MOSFET under radiation strike with 1D electric field distribution and carrier mapping^[76].

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图 9 NITG-MOSFET单粒子烧毁结果和N+岛优化参数设计^[83]　(a)厚度; (b)宽度; (c)第二缓冲层掺杂浓度

Figure 9. SEB results of NITG-MOSFET and optimized design parameters of N+ island^[83]: (a) Thickness; (b) width; (c) N-buffer 2 dopant concentration.

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图 10 在LET = 0.1 pC/μm, V_DS = 650 V条件下, 离子撞击后器件中心的内部电场变化图^[75]　(a) VDMOSFET; (b) DBL-MOSFET; (c) GBL-MOSFET; (d) SBL-MOSFET

Figure 10. The variation of internal electric field at the device center after the ion strike (LET = 0.1 pC/μm, V_DS = 650 V)^[75]: (a) VDMOSFET; (b) DBL-MOSFET; (c) GBL-MOSFET; (d) SBL-MOSFET.

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图 11 1200 V SiC MOSFET结构示意图^[86]　(a)分裂栅与集成肖特基势垒二极管(SBD)结构; (b)扩展型P+源接触结构; (c)多层N型间隔缓冲层结构; (d)扩展型P+源接触与多层N型间隔缓冲层的复合结构

Figure 11. Schematic diagram of 1200 V SiC MOSFET^[86]: (a) With split gate and SBD embedded; (b) with expansion of P+ source contact; (c) with multi-layer N-type interval buffer layer; (d) with expansion of P+ source contact and multi-layer N-type interval buffer layer.

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图 12 抗SEGR的SiC MOSFET器件加固结构示意图　(a) HEC-MOSFET^[91]; (b) BSE-MOSFET^[92]; (c) IM-DTMOSFET^[93]

Figure 12. Hardening structure diagram of SiC MOSFET device against SEGR: (a) HEC-MOSFET^[91]; (b) BSE-MOSFET^[92]; (c) IM-DTMOSFET^[93].

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表 1 平面型SiC MOSFET单粒子效应研究汇总

Table 1. Summary of research on single event effect of planar SiC MOSFET.

器件设计	研究类型	LET/(MeV·cm²·mg^–1)	V_SEB/V	文献
[1200 V] VDMOSFET	Experiment	35.8	350	[6]
[1200 V] VDMOSFET	Experiment	7.7—49.1	580—700	[46]
[1200 V] VDMOSFET	Experiment	0.26—118	200—600	[49]
[1200 V] VDMOSFET	Experiment	70.2	800	[51]
[1200 V] VDMOSFET	Experiment	10—65	500—600	[52]
[1200 V] VDMOSFET	Experiment	81.3	400	[53]
[1200 V] VDMOSFET	Experiment	38.85	400	[54]

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表 2 重离子诱导效应总结(阈值)^[62]

Table 2. Summary of heavy-ion-induced effects (threshold values)^[62].

粒子	LET /(MeV·cm²·mg^–1)	Microdose /V	SELC /V	SEGR /V
Xe	62.5	40	70	120
Kr	32.4	70	120	400
Ni	20.4	90	120	—
Fe	14.53	430	450	500
Ca	13.5	520	530	550

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表 3 沟槽型SiC MOSFET单粒子效应研究汇总

Table 3. Summary of research on single event effect of trench SiC MOSFET.

器件设计	研究类型	LET/(MeV·cm²·mg^–1)	V_SEB/V	文献
[650 V] DTMOSFET	Simulation	151	70	[55]
[1200 V] DTMOSFET	Experiment	81.3	<504	[56]
[1512 V] DTMOSFET	Simulation	15.1	597	[58]
[900 V] TB-QVDMOSFET	Simulation	75.5	478	[64]
[1260 V] CoolSiC Trench MOSFET	Simulation	67.95	600	[65]
[1200 V] TGMOSFET	Experiment	75	500	[66]

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表 4 几种主流的SiC MOSFET单粒子效应加固设计汇总

Table 4. Summary of several mainstream hardening design of SiC MOSFET single event effect.

器件类型	加固方法	加固机理	文献
NITG-MOSFET	多层缓冲层(MBLs)	MBLs可以降低N–漂移层与N+衬底界面处的峰值电场强度, 抑制二次击穿.	[83]
IM-DTMOSFET	p型源极缓冲层(P-SBL)和多缓冲层(MBLs)	P-SBL和MBLs可以缓解高能重离子撞击后瞬态脉冲引起的器件局部温度升高.	[93]
STG-MOSFET	源接触处P+屏蔽区和高K介质材料(HfO₂)	源接触处P+屏蔽区可抑制寄生BJT导通, 高K介电材料可降低栅氧化层的最大电场强度.	[98]
HEC-MOSFET	JFET中间区域P+ 柱和电流扩散层(CSL)	P+柱能去除JFET区域周围积累的多余空穴, CSL可以扩大能量耗散面积以及在高V_DS偏置下提供良好的夹断效果.	[99]
DGF-UMOSFET	接地和浮空p-埋层	p-埋层有效降低栅极氧化界面和衬底界面处的晶格最高温度.	[100]
DT-HJDUMOSFET	集成异质结二极管(HJD)	HJD结构能抑制寄生BJT的导通并且使产生的空穴电流可以有效地泄漏, 提高SEB性能.	[101]
SH-MOSFET	源极侧边多晶硅/ 碳化硅异质结	源极侧边poly-Si区域不仅充当空穴放电的通道, 降低氧化层下方积累的空穴浓度, 增强SEGR电阻, 还能有效降低寄生BJT的电流增益, 改善SEB性能.	[102]

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Vol. 74, Issue 13 - 2025-07-05

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