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二维半导体材料凭借其独特的物理特性与优异的电学性能, 在后摩尔时代集成电路发展中展现出巨大潜力. 开发与二维材料兼容的极性调控方法, 已成为基于二维半导体构建互补逻辑电路、实现低功耗且高稳定性信息处理功能的关键, 有望为持续提升集成电路性能提供新路径. 本研究报道了一种基于一步退火工艺的二维半导体极性调控策略, Pd电极接触的WSe2晶体管的导电特性经退火由n型主导转变为p型主导; 而Cr电极接触的器件则始终保持n型主导的导电特性. 在此基础上, 通过在同一WSe2上选择性制备不同金属材料的源漏电极并结合一步退火工艺, 实现了互补晶体管的单片集成, 进而通过器件互联实现了反相器功能. 在2.5 V的电源电压(Vdd)下, 反相器增益达23, 总噪声容限达2.3 V(0.92 Vdd). 该研究为二维半导体的极性调控提供了全新的技术路径.Two-dimensional (2D) semiconductor materials exhibit tremendous potential for post-Moore integrated circuits due to their unique physical properties and superior electrical characteristics. However, critical challenges in polarity modulation and complementary integration have significantly hindered the practical applications of 2D materials. The development of compatible polarity-modulation techniques has emerged as a critical step in achieving device functional integration for constructing 2D materials-based complementary circuits. This study innovatively proposes a one-step-annealing-driven polarity-modulation strategy for 2D semiconductors. It is demonstrated in this study that the conduction behavior of Pd-contacted WSe2 transistors transitions from n-type to p-type dominance after annealing, while Cr-contacted devices maintain n-type dominance. Based on this polarity-modulation strategy, by selectively fabricating source and drain electrodes with different metal materials (Pd and Cr) on the same WSe2, combined with a one-step annealing process, the monolithic integration of complementary transistors is achieved, thereby realizing inverter function through device interconnection. The fabricated inverters exhibit a high voltage gain of 23 and a total noise margin of 2.3 V(0.92 Vdd) at an applied Vdd of 2.5 V. This work not only establishes a novel technical pathway for polarity modulation in 2D materials but also provides crucial technological support for developing 2D semiconductor-based complementary logic circuits.
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Keywords:
- tungsten diselenide /
- polarity modulation /
- complementary transistors
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图 1 WSe2 FETs的极性调控 (a) 以Pd和Cr作为源漏接触电极的WSe2器件在退火前后的光学照片对比, 其中将退火前后Pd-WSe2与Cr-WSe2器件电极近邻沟道区域分别标记为区域Ⅰ, Ⅱ, Ⅲ和Ⅳ, 比例尺为1 μm; (b) 图(a)中对应区域“Ⅰ—Ⅳ”的拉曼光谱表征结果; 以Pd(c)和Cr(d)为源漏接触电极的背栅结构WSe2 FETs退火前后的转移特性曲线, 施加Vds为3 V, 器件结构示意图如插图所示
Fig. 1. Polarity modulation of WSe2 FETs: (a) Comparative optical micrographs of Pd-contact and Cr-contact WSe2 devices before and after annealing. The electrode-proximal channel zones in Pd-WSe2 and Cr-WSe2 devices are labeled as regions Ⅰ, Ⅱ, Ⅲ and Ⅳ before and after annealing states, respectively, the scale bar is 1 μm. (b) Raman spectrum characterization results of the corresponding regions “Ⅰ–Ⅳ” marked in Figure (a). Transfer characteristic curves of back-gated WSe2 FETs with Pd contact (c) and Cr contact (d) before and after annealing, measured at Vds of 3 V, and the insets illustrate the schematics of device structures.
图 2 基于WSe2的互补FETs的单片集成与电学特性 (a) 在单一WSe2材料上集成互补FETs的器件结构示意图, 经退火操作后, Pd-WSe2 FET表现为p-FET, Cr-WSe2 FET表现为n-FET; (b) p-FET和n-FET的转移特性曲线, 其中红色曲线代表p-FET, 蓝色曲线代表n-FET, 施加的Vds分别为–1 V和1 V; p-FET(c)和n-FET(d)的输出特性曲线, Vg变化范围为0—2.5 V, 变化步长为0.5 V, 施加的Vs分别为3和0 V
Fig. 2. Monolithic integration and electrical characteristics of WSe2-based complementary FETs: (a) Schematic of the integrated complementary FETs on a single WSe2 flake, the annealed Pd-WSe2 FET serves as p-FET and the Cr-WSe2 FET functions as n-FET; (b) transfer characteristic curves of the p-FET (red curve) and n-FET (blue curve), the applied Vds are –1 V and 1 V, respectively; output characteristic curves of the p-FET (c) and n-FET (d), the Vg swept from 0 to 2.5 V with step increments of 0.5 V, and the applied Vs are 3 and 0 V, respectively.
图 3 基于WSe2 FETs构建的互补逻辑反相器及其电学性能 (a) p-FET和n-FET串联组成的互补逻辑反相器的电路图; (b) 反相器的电压传输特性曲线, 所施Vdd范围为1—2.5 V, 变化步长为0.5 V; (c) 基于反相器电压传输特性曲线提取的电压增益; (d) 当Vdd为2.5 V时, WSe2反相器的蝶形电压传输特性曲线
Fig. 3. Construction and electrical characteristics of complementary logic inverter based on WSe2 FETs: (a) Circuit diagram of the complementary logic inverter composed of p-FET and n-FET connected in series; (b) voltage transfer characteristic curves of inverter, the applied Vdd range from 1 to 2.5 V with step increments of 0.5 V; (c) voltage gain extracted from the voltage transfer characteristic curves of the inverter; (d) butterfly voltage transfer characteristic curves of WSe2 inverter at applied Vdd of 2.5 V.
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[1] Desai S B, Madhvapathy S R, Sachid A B, Llinas J P, Wang Q X, Ahn G H, Pitner G, Kim M J, Bokor J, Hu C M, Wong H S P, Javey A 2016 Science 354 99
Google Scholar
[2] Liu Y, Duan X D, Huang Y, Duan X F 2018 Chem. Soc. Rev. 47 6388
Google Scholar
[3] Radisavljevic B, Radenovic A, Brivio J, Giacometti V, Kis A 2011 Nat. Nanotechnol. 6 147
Google Scholar
[4] Wu F, Tian H, Shen Y, Hou Z, Ren J, Gou G Y, Sun Y B, Yang Y, Ren T L 2022 Nature 603 259
Google Scholar
[5] Akinwande D, Huyghebaert C, Wang C H, Serna M I, Goossens S, Li L J, Wong H S P, Koppens F H L 2019 Nature 573 507
Google Scholar
[6] Das S, Sebastian A, Pop E, McClellan C J, Franklin A D, Grasser T, Knobloch T, Illarionov Y, Penumatcha A V, Appenzeller J, Chen Z H, Zhu W J, Asselberghs I, Li L J, Avci U E, Bhat N, Anthopoulos T D, Singh R 2021 Nat. Electron. 4 786
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Rabaey J M (translated by Zhou R D) 2004 Digital Integrated Circuits A Design Perspective (Beijing: Publishing House of Electrnics Industry) pp136–140
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Google Scholar
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