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本文利用密度泛函理论结合非平衡格林函数的第一性原理方法,研究了金属相1T-MoS2和Pd金属为非对称源漏电极的5 nm二维SiC场效应晶体管的输运性质,并系统分析了1T-MoS2电极层数增加以及工作电压缩减对器件工作性能的影响机制.研究结果表明1T-MoS2层数增加会增大器件空穴肖特基势垒高度,但同时提高带边输运系数,二者相互竞争共同影响器件的工作性能.SiC的宽禁带特征可以显著抑制短沟道效应,使所有器件都可以满足关态要求.更重要的是,所有器件在0.64 V工作电压下的亚阈值摆幅都接近60 mV/dec物理极限,且各项工作性能参数均能显著超越国际设备和系统路线图(IRDS)为高性能器件设定的标准.此外,器件的工作电压可以进一步降低至0.52 V,对应的功耗延迟积和延迟时间低至0.086 fJ/μm和0.038 ps,仅为IRDS 标准的14%和4%.本工作提出的非对称源漏电极设计策略不仅很好地解决了现有二维材料场效应晶体管开态电流不高以及短沟道效应制约关态电流的问题,更为后摩尔时代超低功耗纳米电子器件的发展提供了重要解决方案.By using the first-principles method based on density functional theory and non-equilibrium Green's function, we studied the transport properties of 5 nm two-dimensional SiC Field-effect transistors with asymmetric metal phases 1T-MoS2 source and Pd drain electrodes. The influence mechanism of the increase of 1T-MoS2 electrode layers and the decrease of working electrical compression on the device’s performance is systematically analyzed. The Schottky barriers extracted from the zero bias and zero gate voltage transport spectra show that the valence band maximum of SiC in the channel regions of MFET, BFET and TFET are closer to the Fermi level after the source drain electrode is balanced. Therefore, the three devices belong to P-type contact, and the hole Schottky barrier height increases with the increase of the number of 1T-MoS2 layers of the source electrode, which are 0.6, 0.76 and 0.88 eV, respectively. In addition, the increase of 1T-MoS2 layers will also lead to the increase of the density of states in the source electrode, thereby improving the transport coefficient at the band edge. The effect of the two on the transport capacity of the device is opposite, and there is a competitive relationship. The transfer characteristics of devices show that the wide band gap of SiC can significantly suppress the short channel effect, so that all devices can meet the requirements of off state. More importantly, the subthreshold swing of all devices at 0.64 V operating voltage is close to the physical limit of 60 mV/dec. The ON-current of MFET, BFET and TFET can reach 1553, 1601 and 1702 μA/μm under the more stringent IRDS HP standard, and the three performance parameters of intrinsic gate capacitance, power-delay product and delay time can greatly exceed the international road map of equipment and systems (IRDS) standards for high-performance devices. In addition, the working voltage of MFET can be reduced to 0.52 V, and the corresponding power-delay product and delay time are as low as 0.086 FJ/μm and 0.038 ps, which are only 14% and 4% of the IRDS standard. The asymmetric source drain electrode design strategy proposed in this work not only solves the problems of low on state current and short channel effect restricting off state current of existing two-dimensional material Field-effect transistors, but also provides an important solution for the development of ultra-low power nano electronic devices in the post Moore era.
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Keywords:
- Two-dimensional material /
- First principles /
- Field-effect transistor /
- Transfer characteristic /
- quantum interference
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