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In order to improve the discrepancy between specific on-resistance (Ron,sp) and breakdown voltage (BV) of lateral double-diffused metal oxide semiconductor (LDMOS) and enhance the turn-off characteristic, this paper proposes a novel LDMOS device with dual-drift regions and dual-conduction paths, which achieves an ultra-low Ron,sp. The key feature of the proposed device is the introduction of a dual-drift region structure with alternating P-type and N-type regions, combined with planar and trench gates to control the P-type and N-type drift regions, respectively. This configuration enables the formation of two independent electron conduction paths within the drift region. When a positive voltage is applied to the planar gate, a voltage difference is generated between the surface of the P-type drift region and the body of device’s drift. Therefore, under the influence of the voltage difference, the electrons are pulled to the surface of the P-type drift region to invert and form a high-density electron inversion layer that connects the channel and the N+ drain, significantly increasing the electron density during conduction and reducing the Ron,sp. The introduction of the trench gate provides an additional electron disappearance path, which shortens the device's turn-off time (toff). Furthermore, the introduction of the P-type drift region facilitates the recombination of electrons with holes within the P-type drift region, accelerating the electron disappearance process and further reducing the device's toff. Furthermore, the proposed device exhibits a more uniform electric field distribution and higher voltage capability is due to the P+N-N+P+ structure adopted in the PolySi-top layer. During the off-state, both the P+N- junctions and the N+P+ junctions generate electric field peaks at the interfaces. These peaks modulate the electric field distribution across the surface of the drift region. Simulation results indicate that at a BV of 200V, the proposed LDMOS exhibits an Ron,sp of 3.43 mΩ·cm² and a toff of 9 ns. Compared with traditional LDMOS devices, the proposed LDMOS possesses a 90% reduction in Ron,sp and an 11.6% decrease in toff. The proposed device not only achieves an excellent trade-off between Ron,sp and BV but also shortens the toff, demonstrating that the device achieves superior performance.
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Keywords:
- dual-drift /
- dual-conduction paths /
- specific on-resistance /
- breakdown voltage
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图 1 器件结构图 (a)传统LDMOS; (b) PND-DP LDMOS; (c) NND-DP LDMOS
Figure 1. Schematic cross-section: (a) Conventional LDMOS; (b) PND-DP LDMOS; (c) NND-DP LDMOS.
图 2 器件工作原理图 (a) PND-DP LDMOS; (b) NND-DP LDMOS
Figure 2. Schematic of the proposed devices operation: (a) PND-DP LDMOS; (b) NND-DP LDMOS.
图 3 PND-DP LDMOS器件工艺流程图
Figure 3. The fabricate process of PND-DP LDMOS.
图 4 器件输出特性曲线
Figure 4. The Id-Vd curve of these three devices.
图 5 器件漂移区电子浓度分布曲线 (a) PND-DP LDMOS; (b) NND-DP LDMOS
Figure 5. Distribution of the drift electron density: (a) PND-DP LDMOS; (b) NND-DP LDMOS.
图 6 (a)击穿特性曲线; (b)Ntop对器件击穿特性的影响
Figure 6. (a) Breakdown characteristic curve; (b) the impact of Ntop on device breakdown characteristics.
图 7 器件电场分布图 (a) 横向电场; (b)纵向电场
Figure 7. Device electric field distribution: (a) Lateral electric field; (b) vertical electric field.
图 8 N-drift 对器件性能的影响 (a) BV; (b) Ron, sp; (c) FOM
Figure 8. The impact of N-drift on device performance: (a) BV; (b) Ron, sp; (c) FOM.
图 9 本文所提出的PND-DP LDMOS与其他器件的Ron, sp, -BV比较
Figure 9. Comparison of Ron, sp, -BV between the proposed PND-DP LDMOS and others.
图 10 器件动态特性 (a)测试电路结构; (b)关断特性曲线
Figure 10. Device dynamic characteristics: (a) Test circuit structure; (b) turn-off characteristic curve.
表 1 器件仿真中的关键参数
Table 1. Key parameters of devices’ simulation.
参数符号 参数含义 传统 PND-DP NND-DP Tox/μm 氧化层厚度 0.1 0.1 0.1 LD/μm 漂移区长度 20 8.5 8.5 TDP/TDN2 /μm P-drift(N-drift2)的厚度 2 2 2 TDN/TDN1/μm N-drift(N-drift1)的厚度 — 3 3 Tb/μm N-buffer的厚度 — 3.5 3.5 LCH/μm 沟道长度 1.5 1.5 1.5 Tt/μm 槽栅的深度 — 2.1 2.1 NDP/NDN2/cm–3 P-drift(N-drift2)的掺杂浓度 — 1×1015 1×1015 NDN/NDN1/cm–3 N-drift(N-drift1) 的掺杂浓度 7.5×1015 2.5×1015 1.5×1015 Ntop/cm–3 N-top的掺杂浓度 — 1×1015 1×1015 Nsub/cm–3 衬底的掺杂浓度 3×1014 3×1014 3×1014 
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表 2 PND-DP LDMOS与其他器件的Ron, sp, BV, FOM
Table 2. Ron, sp, BV, and FOM of PND-DP LDMOS compared with other devices.
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