忆阻类脑计算

温新宇; 王亚赛; 何毓辉; 缪向水

doi:10.7498/aps.71.20220666

摘要

随着深度学习的高速发展, 目前智能算法的飞速更新迭代对硬件算力提出了很高的要求. 受限于摩尔定律的告竭以及冯·诺伊曼瓶颈, 传统CMOS集成无法满足硬件算力提升的迫切需求. 利用新型器件忆阻器构建神经形态计算系统可以实现存算一体, 拥有极高的并行度和超低功耗的特点, 被认为是解决传统计算机架构瓶颈的有效途径, 受到了全世界的广泛关注. 本文按照自下而上的顺序, 首先综述了主流忆阻器的器件结构、物理机理, 并比较分析了它们的性能特性. 然后, 介绍了近年来忆阻器实现人工神经元和人工突触的进展, 包括具体的电路形式和神经形态功能的模拟. 接着, 综述了无源和有源忆阻阵列的结构形式以及它们在神经形态计算中的应用, 具体包括基于神经网络的手写数字和人脸识别等. 最后总结了目前忆阻类脑计算从底层到顶层所遇到的挑战, 并对该领域后续的发展进行了展望.

关键词:

Abstract

With the rapid development of deep learning, the current rapid update and iteration of intelligent algorithms put forward high requirements for hardware computing power. Limited by the exhaustion of Moore’s law and the von Neumann bottleneck, the traditional CMOS integration cannot meet the urgent needs of hardware computing power improvement. The utilization of new device memristors to construct a neuromorphic computing system can realize the integration of storage and computing, and has the characteristics of extremely high parallelism and ultra-low power consumption. In this work, the device structure and physical mechanism of mainstream memristors are reviewed in bottom-to-top order firstly, and their performance characteristics are compared and analyzed. Then, the recent research progress of memristors to realize artificial neurons and artificial synapses is introduced, including the simulation of specific circuit forms and neuromorphic functions. Secondly, in this work, the structural forms of passive and active memristive arrays and their applications in neuromorphic computing, including neural network-based handwritten digits and face recognition, are reviewed. Lastly, the current challenges of memristive brain-like computing from the bottom to the top, are summarized and the future development of this field is also prospected.

Keywords:

作者及机构信息

1.
华中科技大学集成电路学院, 信息存储材料及器件研究所, 武汉　430074

2.
江城实验室, 武汉　430205

通信作者: 何毓辉, heyuhui@hust.edu.cn ; 缪向水, miaoxs@hust.edu.cn

基金项目: 国家重点研发计划(批准号: 2019YFB2205100)和国家自然科学基金(批准号: 92064012, 61974051, 61874164, 51732003)资助的课题

Authors and contacts

1.
Institute of Information Storage Materials and Devices, School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan 430074, China

2.
Hubei Yangtze Memory Laboratories, Wuhan 430205, China

Corresponding author: He Yu-Hui, heyuhui@hust.edu.cn ; Miao Xiang-Shui, miaoxs@hust.edu.cn

Funds: Project supported by the National Key R&D Program of China (Grant No. 2019YFB2205100) and the National Natural Science Foundation of China (Grant Nos. 92064012, 61974051, 61874164, 51732003)

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施引文献

图 1 综述各节内容总括

Fig. 1. Schematic organization of each section of the review work

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图 2 根据$ t _{{\rm{set}}} $和$ t _{\rm{r}} $顺序排列的v-ECM型扩散忆阻器的不同应用领域^[25]

Fig. 2. Different areas of applications of v-ECM-type diffusive memristors arranged according to exemplary requirements in $ t _{{\rm{set}}} $ and $ t _{\rm{r}} $^[25]

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图 3 (a) Oxide RRAM的MIM结构原理图; (b)非极性和(c)双极性不同原理的阻变I-V特性曲线图^[34]

Fig. 3. (a) Schematic of MIM structure for metal-oxide RRAM, and schematic of metal-oxide memory’s I-V curves for (b) unipolar and (c) bipolar^[34]

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图 4 (a) PCRAM相变的脉冲操作示意图^[46]; (b) 目前主流合金材料的三元Ge∶Sb∶Te相图^[48]

Fig. 4. (a) Schematic of pulse operation leading to PCRAM phase transition^[46]; (b) the most popular alloy line in ternary Ge∶Sb∶Te phase diagram^[48]

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图 5 (a) STT-MRAM和SOT-MRAM的单元结构图^[63]; (b) STT-MRAM的置态和重置操作原理图^[64]

Fig. 5. (a) Bit-cell for STT-MRAM and SOT-MRAM^[63]; (b) schematic illustration of the STT switching mechanism to achieve 1 and 0 states^[64].

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图 6 (a) FTJ结构及铁电层BaTiO₃晶体结构示意图; TER效应: (b) P-E特性曲线; (c) I-V特性曲线^[77]

Fig. 6. (a) FTJ structure and schematic diagram of the ferroelectric layer BaTiO₃ crystal structure; TER effect: (b) P-E characteristic curve; (c) I-V characteristic curve^[77]

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图 7 LTP的忆阻器实现　(a)使用忆阻器作为神经元之间的突触的概念示意图; (b)忆阻器对编程脉冲的响应^[101]; (c) Pt/LiAlO_x/TiN忆阻器在不同初始电导状态下的电导调制性能textsuperscript^[102]; (d) DW-MTJ人工突触的侧视和俯视图; (e) DW-SOT和DW-STT器件的测试更新线性度和对称性^[103]

Fig. 7. Memristor implementation of LTP: (a) Schematic illustration of the concept of using memristors as synapses between neurons; (b) memristor response to programming pulses^[101]; (c) conductance modulation performance at different initial conductance states of Pt/LiAlO_x/TiN memristor^[102]; (d) side and top profile of DW-MTJ artificial synapse; (e) update linearity and symmetry with experimental data from DW-SOT and DW-STT devices^[103]

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图 8 STP的忆阻器实现　(a)测试过程中通过忆阻器的连续电流变化; (b)图(a)中矩形区域的特写图; (c)电导转换速率与刺激速率的关系图, 在不同脉冲间隔条件下, 每次刺激脉冲后通过忆阻器的电流^[109]; (d) ITO/PVPy-Au NPs/Al RRAM器件的结构和Au NPs的HRTEM图像; 在(e) 2次和(f)10次不同脉冲间隔的脉冲之间的器件电流变化图^[111]

Fig. 8. Memristor implementation of STP: (a) The corresponding current through the memristor data recorded continuously throughout the test. (b) A close-up view of the rectangular area in panel (a). (c) Dependence of the transition efficiency on stimulation rate. Current through the memristor recorded after each stimulation pulse, at different pulse interval conditions^[109]. (d) The structure of ITO/PVPy–Au NPs/Al RRAM device and the HRTEM image of Au NPs. Current change between (e) two pulses and after (f) 10 pulses with different pulse intervals^[111]

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图 9 SRDP的忆阻器实现　(a)具有SRDP特性的生物突触示意图^[116]; (b) WO_x 基忆阻器对不同频率下连续编程脉冲序列(1 V, 1 ms, 蓝线)的响应; (c) 在经历了不同程度的激活后, 忆阻器电流随刺激频率的变化. 由5个不同频率的脉冲(1.2 V, 1 ms) 组成的不同频率的脉冲序列对忆阻器进行编程^[118]

Fig. 9. Memristor implementation of SRDP: (a) Schematic diagram of a biological synapse with SRDP activities^[116]; (b) WO_x based memristor response to consecutive programming pulse trains (1 V, 1 ms, blue lines) at different frequencies; (c) memristor current change as a function of the stimulation frequency after the memristor has been experienced to different levels of activities. Pulse trains consisting of five pulses (1.2 V, 1 ms) with different repetition frequencies were used to program the memristor^[118]

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图 10 STDP的忆阻器实现　(a) STDP特性展示图^[120]; (b) 利用TDM和脉冲幅度调制的STDP实现方案, 突触前脉冲振幅分别为–1.4, 1, 0.9, 0.8, 0.7和0.6 V, 突触后脉冲振幅分别为–1, 1.4, 1.3, 1.2, 1.1和1 V; (c)利用图(b)中的方法实测的器件STDP曲线^[124]; (d) 忆阻权重的变化与突触前后脉冲相对时间的关系, Δt = t_post – t_pre; (e)脉冲相对时间影响忆阻器的原理示意图^[118]

Fig. 10. Memristor implementation of STDP: (a) Defining spike-timing-dependent plasticity^[120]; (b) STDP realization schemes developed with TDM and pulse amplitude modulation. The pulse amplitudes for the prespike are –1.4, 1, 0.9, 0.8, 0.7, and 0.6 V, consecutively, and for the postspike, they are –1, 1.4, 1.3, 1.2, 1.1, and 1 V, consecutively. (c) Measured STDP curve of the memristors utilizing method described in panel (b)^[124]. (d) Memristor weight change as a function of the relative timing between the pre- and postsynaptic pulses, Δt = t_post – t_pre. (e) Simulation results illustrating how relative timing of the pulses affects memristor weight^[118]

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图 11 (a)生物神经元的结构; (b)基于兴奋性和抑制性电位的神经元膜电位变化^[130]

Fig. 11. (a) Structure of the biological neuron; (b) membrane potential change of the neuron depending on the excitatory and inhibitory potentials^[130].

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图 12 非易失器件实现神经元　(a)漏电积分点火神经元的模型展示图; (b)输入间隔640 ms的兴奋性脉冲序列时得到的输出电流图^[135]; (c) PCMO RRAM的器件结构图; (d)施加–2.3 V置态电压时显示出的3个不同阶段的瞬时电流值; (e)应用预设脉冲序列的瞬态实验电流值^[136]

Fig. 12. Neurons implemented by nonvolatile Devices: (a) Basic representation of leaky integrate-and-fire neuronal model; (b) the output current measured after excitatory input pulse with the time separated of 640 ms^[135]; (c) device schematic of PCMO RRAM; (d) SET current transient at –2.3 V showing 3 regions of operation; (e) experimental Current transient for the applied sequence of SET pulses^[136]

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图 13 易失型器件实现神经元　(a)所提出的神经元电路的示意图; (b)电容上的电压变化图; (c)输出神经元的发放脉冲具有相应的不应期和积分时间^[139]; (d) 带有两个W/WO₃/PEDOT: PSS/Pt忆阻器件的具体神经元电路; (e)利用电路得到的单脉冲生物积分点火; (f)利用电路得到的连续脉冲生物积分点火^[141]; (g) 神经元电路原理图, 输入电压脉冲来自信号发生器; (h)基于CuS/GeSe的神经元电路在脉冲幅度为2 V、脉冲宽度为7.5 ms的输入电压脉冲序列下的随机脉冲发放事件^[142]

Fig. 13. Neurons implemented by volatile Devices: (a) Schematic illustration of the proposed neuron circuit; (b) the voltage variation across the capacitor; (c) the output neuron spike with the corresponding refractory period and integration moment^[139]; (d) the electrical circuit with two W/WO₃/PEDOT:PSS/Pt memristive devices; (e) spatial integration and bioinspired fire realized with the circuit; (f) temporal integration and bioinspired fire realized with the circuit^[141]; (g) schematic of neuronal circuit where the input voltage pulses originate from the signal generator; (h) the experimentally measured stochastic spike events of the CuS/GeSe based neuronal circuit under an input voltage pulse train with pulse height 2 V and duration 7.5 ms^[142]

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图 14 无源忆阻阵列神经形态计算　(a) 典型的二维Crossbar阵列潜行电流读取扰动问题示意图 (细蓝线表示读取电流、粗红线表示潜行电流)^[14]; (b) 利用10 × 6忆阻器Crossbar实现的单层感知机网络; (c) 针对特定输入图片(程式化的字母“z”)的分类操作示例^[145]; (d) 两个20 × 20的crossbar阵列实现双层神经网络的示意图^[146]

Fig. 14. Passive memristive arrays for neuromorphic computing: (a) A schematic diagram of the typical 2D Crossbar array showing the read disturbance problem by the presence of sneak current (The thin blue line represents reading current, and the thick red line represents sneak current)^[14]; (b) an implementation of a single-layer perceptron using a 10 × 6 fragment of the memristive crossbar; (c) an example of the classification operation for a specific input pattern (stylized letter ‘z’)^[145]; (d) a schematic diagram of two 20 × 20crossbar arrays implementing a two-layer neural network^[146].

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图 15 1S1P无源忆阻阵列神经形态计算　(a)存算一体的1S1P结构对crossbar阵列实现形式; (b)差分对结构示意图; (c)神经网络的输入前向传播过程; (d)神经网络更新示意图^[149]

Fig. 15. 1S1P passive memristive array for neuromorphic computing: (a) In-memory computing implemented using dense crossbar arrays of 1S1P pairs; (b) structure diagram of differential pairs; (c) the input forward propagation process of the neural network; (d) schematic diagram of neural network update^[149].

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图 16 3D无源忆阻阵列神经形态计算　(a) 两个Pt/Al₂O₃/TiO_2–x/TiN/Pt型忆阻器堆叠结构的等效电路^[150]; (b) 共享位线结构的3D Crossbar阵列^[14]; (c) 整个电路利用FPGA控制的继电器矩阵实现Crossbar的自动控制测试; (d)新的三维VRRAM结构的高分辨率透射显微镜图象; (e) 三维VRRAM架构中一次卷积操作的电流方向原理图^[154]

Fig. 16. 3D passive memristive array for neuromorphic computing: (a) Equivalent circuit for two Pt/Al₂O₃/TiO_2–x/TiN/Pt memristors in the stacked configuration^[150]; (b) a schematic diagram showing the shared bit line structure in cross-line type 3D Crossbar array^[14]; (c) FPGA-controlled relay matrix to achieve test automation; (d) HRTEM image of the novel 3D VRRAM structure; (e) the schematic of the 3D VRRAM architecture and current flow for one convolution operation^[154].

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图 17 1T1R有源忆阻阵列神经形态计算　(a)用于原位学习的忆阻平台. 从左到右分别是: 带有晶体管阵列的晶圆、芯片特写图、1T1R单元的显微镜图像、1T1R单元的SEM图像、Ta /HfO₂/Pt忆阻器的横截面TEM图像^[157]. (b)单层神经网络在1T1R阵列上的映射. (c)使用CMOS兼容制造工艺制备的1024 1T1R单元的阵列显微镜图. (d)训练过程流程图. (e)模型映射到输入及并行读取操作的原理图^[160]

Fig. 17. 1T1R passive memristive array for neuromorphic computing: (a) Memristive platform for in situ learning. From left to right are: A wafer with transistor arrays, close-up of chip image, microscope image of 1T1R cell, SEM of an individual 1T1R cell, cross-sectional TEM image of the Ta/HfO₂/Pt memristor^[157]. (b) Mapping of a one-layer neural network on the 1T1R array. (c) The micrograph of a fabricated 1024-cell-1T1R array using fully CMOS compatible fabrication process. (d) The training process flow chart. (e) The schematic of parallel read operation and how a pattern is mapped to the input^[160]

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表 1 不同类型忆阻器件参数指标比较

Table 1. Comparison of parameter specifications of different types of memristors

参数指标	RRAM	PCRAM	MRAM	FeRAM
切换速度/ps	85^[43]	700^[54]	210^[85]	4000^[86]
开关比	10⁷^[87]	10⁶^[88]	< 10^[67,89]	10⁷^[84]
室温保持特性/a	> 1000^[44]	> 10^[90]	> 10^[91]	> 10^[76,81]
耐擦写次数	10¹²^[45]	10¹¹^[92]	5 × 10¹⁴^[66]	10¹¹^[82]
开关功耗/fJ	115^[42]	50^[93]	10^[94]	10^[95]

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