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In this paper, graphene field effect transistors (GFETs) with the top-gate structure are taken as the research object. The electrical stress reliabilities are studied under different bias voltage conditions. The electrical pressure conditions are gate electrical stress (VG = –10 V, VD = 0 V, and VS = 0 V), drain electric stress (VD = –10 V, VG = 0 V, and VS = 0 V), and electrical stresses applied simultaneously by gate voltage and drain voltage (VG = –10 V, VD = –10 V, VS = 0 V). Using a semiconductor parameter analyzer, the transfer characteristic curves of GFETs before and after electrical stress are obtained. At the same time, the carrier migration and the Dirac voltage VDirac degradation are extracted from the transfer characteristic curves. The test results show that under different electrical pressures, the carrier mobility of GFETs degrades continuously with the increase of electric stress time. Different electrical pressure conditions have varying effects on the drift direction and degradation of VDirac: gate electrical stress and drain electrical stress cause VDirac drift of the device in opposite directions, and the gate electrical stress is greater than the electrical stress applied by both gate voltage and drain voltage, leading to VDirac degradation of GFETs. An analysis of the causes indicates that different electrical stresses produce different electric field directions in the device, which can affect the carrier concentration and movement direction. Electrons and holes in the channel are induced and tunnel into the oxide layer, and they are captured by trap charges in the oxide layer and at the interface between graphene and oxide, forming oxide trap charges and interface trap charges. This is the main reason for reducing carrier mobility of GFET. Different electric field directions under different electric stresses produce positively charged trap charges and negatively charged trap charges. The difference in the type of trap charge banding is the main reason for the different directions of VDirac drift in GFETs. When both trap charges coexist, they have a canceling effect on the VDirac drift of the GFETs. Finally, by combining TCAD simulation the simulation model of the influence of electrical stress induced trap charge on the VDirac generation of GFET is further revealed. The result demonstrates that the differences in the type of trap charge banding have different degradation effects on the VDirac of GFETs. The related research provides data and theoretical support for putting graphene devices into practical application.
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Keywords:
- graphene field effect transistors /
- electrical stress /
- VDirac /
- carrier mobility
1. Introduction
Since its invention, graphene has attracted great attention for its excellent properties such as high mobility, high thermal conductivity and high mechanical strength. [ 1 – 3 ] Because of its excellent performance, graphene field effect transistors (GFETs) have great potential applications in devices and circuits, so some theoretical and practical problems about GFETs have been studied. [ 4 , 5 ] Among them, the reliability of GFET is a research focus. Graphene material is a single atomic layer with a very high specific surface area, and the charges are all on its surface, which is very vulnerable to the external environment. [ 6 , 7 ] The most striking manifestation is the Dirac voltage ( V Dirac ) movement, V Dirac Represents the voltage value at the Dirac point where the conduction and valence bands of graphene meet, when V G ＞ V Dirac The carriers in graphene are electrons when V G ＜ V Dirac The carriers in graphene are holes. Therefore V Dirac The position of the GFET is one of the most important information, so what factors affect the GFET? V Dirac Mobile has always been a matter of great concern. [ 8 ] .
In recent years, researchers have conducted experimental studies on the reliability of GFETs. 2014, Feng et al. [ 9 ] The effects of temperature and gate scanning range on the electrical characteristics of GFET with back gate structure are studied. It is found that the Dirac voltage of graphene V Dirac With the increase of temperature, the hysteresis curve of GFET gradually moves from 0 V to 0 V. With the increase of temperature and gate voltage scanning range, the hysteresis curve of GFET is similar to that of 0 V. V Dirac They attributed the hysteresis to the combined effects of temperature and gate voltage, the generation of interface trap charges in GFET with back-gate structure, and the redox reaction on the surface of graphene/oxide layer and the displacement of ions in the oxide layer. 2017, Zhang et al. [ 10 ] The dependence of buried-gate GFET transfer characteristics on gate voltage is studied. The experimental results show that the continuous positive or negative scanning of gate voltage will increase the voltage at the Dirac point when testing the transfer characteristics of GFET. Before testing the transfer characteristics of GFET, the increase of the holding time of gate voltage will gradually shift the Dirac voltage to the positive direction. It is pointed out that the magnitude of Dirac voltage is related to the magnitude of gate V..
To sum up, the reliability study of GFET is insufficient for the electrical stress experiment of GFET with top gate structure under different bias voltages. Therefore, the electrical stress experiment of GFET with top gate structure under different bias voltages is carried out in this paper to study the degradation law of electrical performance of GFET. On this basis, the damage mechanism is studied by TCAD numerical simulation.
2. Description of experiment
The research object is the graphene field effect transistor with top gate structure. The device structure such as Fig. 1 The graphene size of the GFET is 100 μm × 100 μm, and the gate oxide is 20 nm thick Al 2 O 3 , the substrate is composed of p-type Si and 90 nm thick SiO 2 Single-layer graphene was grown and transferred by chemical vapor deposition (CVD) and polymer-assisted transfer.
The electrical stress experiment and electrical parameter test were carried out by B1500 semiconductor analyzer. The transfer characteristic curve of GFET was tested for many times. The conditions of transfer characteristic curve test were as follows: gate voltage V G Scan range – 5 — + 5 V, source voltage V S Ground, drain voltage V D Gradually increase from 20 mV. For example, Fig. 2 As shown, as the drain voltage is gradually increased, the GFET V Dirac Gradually drift to the positive direction, which indicates that the hole doping gradually increases, the P-type doping gradually increases, and the N-type doping gradually decreases [ 11 , 12 ] The current of the GFET increases gradually, because the increasing voltage generates a stronger and stronger electric field, and the enhanced electric field gives enough energy to the electrons, so that the electrons can break away from the graphene and escape from the graphene, resulting in enhanced hole doping in the device, increased carrier concentration, and increased current. [ 13 , 14 ] The increased current will cause the temperature of graphene to rise, the vibration of the lattice to become more and more intense, and the number of escaping electrons to increase. [ 15 , 16 ] As a result, the hole doping of graphene is enhanced, the carrier concentration is increased, and the current is increased.
图 2 GFET的转移特性曲线在不同漏极电压下的变化趋势Fig. 2. The variations of the transfer characteristic curve of GFET under different drain voltages.The bias voltage conditions of the electric stress experiment are divided into three groups, namely, the grid electric stress ( V G = –10 V, V D = 0 V, V S = 0 V), drain electrical stress ( V G = 0 V, V D = –10 V, V S = 0 V), simultaneous gate and drain voltage applied electrical stress ( V G = –10 V, V D = –10 V, V S = 0 V). The total duration of the electric stress test is 1000 s, and the electric stress period includes 5 test points. When the cumulative time of the electric stress reaches the test point, the semiconductor analyzer will automatically test the transfer characteristic curve of the GFET once under the set transfer characteristic curve test conditions, and save the data. The test conditions of the electrical stress test are as follows: Table 1 Shown.
表 1 电应力实验测试条件Table 1. Electrical stress test conditions.偏置电压条件 电应力测试时间点 转移特性曲线测试条件 栅极电应力(VG = –10 V, VD = 0 V, VS = 0 V) 0 s, 100 s, 300 s, 500 s, 1000 s VG 从–5 V扫到5 V, VD 为20 mV, VS 接地 漏极电应力 (VG = 0 V, VD = –10 V, VS = 0 V) 栅极电压与漏极电压同时施加的电应力(VD = –10 V, VD = –10 V, VS = 0 V) 3. Results and analysis of the experiment
Fig. 3 — Fig. 5 The variation trend of the transfer characteristic curve of the GFET with the electrical stress accumulation time to 1000 s under three different bias voltages. Fig. 3 As shown, a GFET is electrically stress at that gate ( V G = –10 V, V D = 0 V, V S = 0 V), the transfer characteristic curve of the device gradually moves to the negative direction with the gradual accumulation of electrical stress time. V Dirac Drift in the negative direction, – 2 V before the electrical stress test, – 4.46 V after the electrical stress test, a change of 2.46 V.
图 3 栅极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势Fig. 3. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under gate voltage bias condition.
图 5 栅极和漏极电压同时施加的电应力下, GFET转移特性曲线随电应力累积时间的变化趋势Fig. 5. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under the condition of electrical stress applied by both the gate and drain voltages.
图 4 漏极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势Fig. 4. Variations of GFET transfer characteristic curves with the accumulation time of electrical stress under drain voltage bias conditions.Such as Fig. 4 As shown, that electrical stress at the drain of the GFET ( V G = 0 V, V D = –10 V, V S = 0 V), the transfer characteristic curve gradually moves to the positive direction. V Dirac Drift in the positive direction, – 2.48 V before electrical stress test and – 1.94 V after electrical stress test, a change of 0.54 V. GFET device V Dirac The drift direction is opposite to that of the gate electrical stress. The reason may be the difference of the types of trapped charges produced by the electrical stress under different voltage biases.
如图5所示, GFET在栅极和漏极电压同时 施加的电应力(VG = –10 V, VD = –10 V, VS = 0 V)作用下, 转移特性曲线逐渐向负方向移动. VDirac向负方向漂移, 电应力测试前为–2.5 V, 电应力测试后为–3.68 V, 变化量为1.18 V, 对比发现变化量明显要小于栅极电应力条件下的变化量.
图6给出了GFET的VDirac在两种不同的偏置电压条件下(栅极电应力、栅极和漏极电压同时施加的电应力)随电应力累积时间的变化趋势. 对比GFET在两种不同的偏置电压条件下VDirac的变化量, 发现栅极电应力诱导器件VDirac的退化趋势更加明显. 这可能是因为在栅极和漏极电压同时施加的电应力实验中产生的两种带电类型的陷阱电荷, 引起VDirac的漂移, 产生相互抵消的作用, 导致VDirac退化程度减小.
图 6 VDirac随着电应力累积时间的变化趋势Fig. 6. The variations of VDirac with the accumulation time of electrical stress.计算GFET在不同偏置电压条件下的电应力实验中, 每个时间测试点对应的载流子迁移率. GFET的跨导Gm与载流子迁移率的关系如(1)式所示[17,18]:
μ=LW⋅GmCG⋅VD, (1) 其中, μ为载流子迁移率, L/W为长宽比, CG为栅介质的电容, VD为漏极电压, 跨导Gm为转移特性曲线的斜率. 详细计算参数L/W长宽比为1, CG栅介质电容为3.54×10–7 F/cm2, VD漏极电压为20 mV. 如图7所示, 不同偏置电压条件下的电应力实验中, GFET的空穴迁移率和电子迁移率均随着电应力累积时间的延长而逐渐降低. 载流子迁移率与氧化物陷阱电荷之间的关系为[19]:
图 7 载流子迁移率随电应力累积时间的变化趋势 (a)空穴迁移率随电应力累积时间的变化趋势; (b)电子迁移率随电应力累积时间的变化趋势Fig. 7. The variations of carrier mobility with the accumulation time of electrical stress: (a) The variations of hole mobility with the accumulation time of electrical stress; (b) the variations of electron mobility with the accumulation time of electrical stress.1μ=1μc(Not,Qgc)+1μSR(Eeff), (2) μ−1c=α(Not/N0)(11+Qgc/Q0)β, (3) 其中, μc为受库仑散射作用的载流子迁移率, Not为氧化物陷阱电荷, μSR为受短程散射影响的载流子迁移率, Qgc为电荷密度, Eeff为有效电场强度, α, β, N0, Q0为拟合参数. 由(2)式和(3)式可以得出, 载流子迁移率的退化是由于在电应力实验中产生了氧化物陷阱电荷, 增加了散射位点, 导致库仑散射作用增强, 载流子迁移率降低[17–20].
μ=μ01+αΔNit, (4) 其中μ为实验后的载流子迁移率, ΔNit为新产生的界面陷阱电荷, μ0为实验前的载流子迁移率. 由(4)式得出, 新产生的界面陷阱电荷导致载流子迁移率的降低.
GFET在不同偏置电压条件下的电应力实验中, 产生了氧化物陷阱电荷和界面陷阱电荷, 增加了散射位点, 其库仑散射增强. 导致GFET的电子迁移率和空穴迁移率均随着电应力累积时间的延长而逐渐降低.
4. 损伤机理与模拟仿真
对于栅极电应力, 栅极电压为负, 电场方向垂直于沟道并指向栅极, 使得石墨烯沟道中的空穴浓度增大, 同时在负栅压的作用下, 空穴会隧穿经过石墨烯/栅极氧化层的界面并进入栅极氧化层中, 被材料里的缺陷俘获, 形成带正电荷的氧化物陷阱电荷. 并且沟道中的空穴受电场的影响会累积在石墨烯/栅极氧化层的界面处, 导致界面陷阱更容易俘获空穴, 形成带正电荷的界面陷阱电荷. 产生的陷阱电荷的带电类型一致, 对器件产生叠加效果, 导致GFET的VDirac向负方向漂移量更大, 退化程度更加明显[23–25].
对于漏极电应力, 漏极一端电压为负, 存在由沟道指向漏极的电场方向, 使得石墨烯沟道中的电子浓度增大, 导致石墨烯/氧化层界面处的陷阱更容易俘获电子[10,24], 形成带负电荷的界面陷阱电荷, 导致GFET的VDirac向正方向移动. 栅极电应力与漏极电应力产生的陷阱电荷带电类型不同, 因此造成GFET的VDirac漂移方向相反.
对于栅极和漏极电压同时施加的电应力, 在器件中既有垂直于沟道并指向栅极的电场, 也存在由沟道指向漏极的电场. 使得器件沟道中的空穴浓度和电子浓度均有所增大, 同时在电场的作用下, 空穴会隧穿进入栅极氧化层中形成带正电荷的氧化物陷阱电荷, 在石墨烯/栅极氧化层的界面形成带正电荷的界面陷阱电荷. 电子更容易被石墨烯/氧化层界面处的陷阱俘获, 形成带负电荷的界面陷阱电荷. 因此产生的陷阱电荷所带电类型不同, 对GFET的VDirac的漂移具有相互抵消的效果. 所以在栅极和漏极电压同时施加的电应力作用下, GFET的VDirac的漂移量小于栅极电应力条件下的漂移量, 退化程度减小.
为了更好地解释陷阱电荷带电类型的差异会对顶栅GFET器件VDirac的漂移方向和退化程度产生不同的影响. 结合TCAD仿真工具研究陷阱电荷对GFET的影响, 在TCAD仿真工具中建立顶栅GFET器件的二维结构模型, 石墨烯沟道长度为100 μm, 石墨烯材料则是通过修改多晶硅的材料参数完成代替[26,27]. 仿真过程中, 在GFET的石墨烯/氧化层界面处加入带正电荷的固定陷阱电荷和带负电荷的固定陷阱电荷, 用来模拟在不同偏置电压条件下, 电应力产生陷阱电荷带电类型的差异对GFET的VDirac退化影响.
图8为TCAD仿真结果, 给出了带不同电性的固定陷阱电荷对GFET的转移特性曲线的影响. 如图8(a)所示, 随着带正电荷的固定陷阱电荷浓度的升高, 器件的转移特性曲线逐渐向负向移动, VDirac也逐渐向负方向漂移. 如图8(b)所示, 随着带负电荷的固定陷阱电荷浓度的升高, 器件的转移特性曲线逐渐向正方向移动, VDirac也逐渐向正方向漂移. 对比TCAD仿真结果, 证明陷阱电荷带电类型的差异是导致GFET的VDirac向不同的方向漂移的原因. 为了验证带不同电性的陷阱电荷会对GFET的VDirac漂移量有抵消的效果, 图8(c)中最右边的黑色转移特性曲线未添加固定陷阱电荷, 其余的转移特性曲线添加了相同浓度的带正电荷的固定陷阱电荷. 随着带负电荷的固定陷阱电荷浓度从0 cm–2逐渐增大, 图中的转移特性曲线逐渐向正方向移动, 逐渐靠近未添加固定陷阱电荷的转移特性曲线. 通过TCAD仿真结果发现, 在带正电荷的固定陷阱电荷和带负电荷的固定陷阱电荷共同作用下, GFET的VDirac漂移量逐渐减小. 证明带不同电性的陷阱电荷对GFET的VDirac漂移量会产生抵消作用.
图 8 TCAD仿真结果 (a)带正电荷的固定陷阱电荷对GFET转移特性曲线的影响; (b)带负电荷的固定陷阱电荷对GFET转移特性曲线的影响; (c)带正电荷和带负电荷的固定陷阱电荷同时对GFET转移特性曲线的影响Fig. 8. TCAD simulation results: (a) Effect of a positively charged fixed trap charge on the transfer characteristic curve of GFET device; (b) effect of negatively charged fixed trap charge on the transfer characteristic curve of GFET device; (c) the effect of both positively charged and negatively charged fixed trap charges on the transfer characteristic curve of GFET devices.5. 结 论
本文研究了顶栅结构的GFET器件在不同的电应力条件作用下, 器件电学性能的退化规律. 发现GFET的载流子迁移率随着电应力累积时间的延长不断退化, 但不同偏置电压条件的电应力作用下, GFET的VDirac的漂移方向和退化程度不同. 分析认为, 不同偏置电压条件的电应力作用会在GFET中产生不同方向的电场, 影响沟道中载流子浓度和分布. 在电场方向的作用下, 空穴和电子隧穿进入氧化层, 被材料中的缺陷俘获, 形成氧化物陷阱电荷, 并且还会促使石墨烯/氧化层界面处的陷阱俘获空穴和电子, 形成界面陷阱电荷, 这是造成GFET的载流子迁移率和VDirac退化的主要原因. 同时产生的陷阱电荷所带电类型的差异, 是导致GFET的VDirac的漂移方向和退化程度不同的主要原因. 结合TCAD仿真模拟表明, 带正电荷的陷阱电荷导致GFET的VDirac向负方向漂移, 而带负电荷的陷阱电荷会导致GFET的VDirac向正方向漂移, 并且当两种陷阱电荷同时存在时, 会对GFET的VDirac漂移量产生抵消作用, 证明陷阱电荷的带电类型差异对GFET的VDirac产生不同的退化影响, 为GFET在实际应用中提供参考和帮助.
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图 1 器件结构示意图
Figure 1. Device structure diagram.
图 2 GFET的转移特性曲线在不同漏极电压下的变化趋势
Figure 2. The variations of the transfer characteristic curve of GFET under different drain voltages.
图 3 栅极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势
Figure 3. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under gate voltage bias condition.
图 5 栅极和漏极电压同时施加的电应力下, GFET转移特性曲线随电应力累积时间的变化趋势
Figure 5. Variations of GFET transfer characteristic curve with the accumulation time of electrical stress under the condition of electrical stress applied by both the gate and drain voltages.
图 4 漏极电应力下, GFET的转移特性曲线随电应力累积时间的变化趋势
Figure 4. Variations of GFET transfer characteristic curves with the accumulation time of electrical stress under drain voltage bias conditions.
图 6 VDirac随着电应力累积时间的变化趋势
Figure 6. The variations of VDirac with the accumulation time of electrical stress.
图 7 载流子迁移率随电应力累积时间的变化趋势 (a)空穴迁移率随电应力累积时间的变化趋势; (b)电子迁移率随电应力累积时间的变化趋势
Figure 7. The variations of carrier mobility with the accumulation time of electrical stress: (a) The variations of hole mobility with the accumulation time of electrical stress; (b) the variations of electron mobility with the accumulation time of electrical stress.
图 8 TCAD仿真结果 (a)带正电荷的固定陷阱电荷对GFET转移特性曲线的影响; (b)带负电荷的固定陷阱电荷对GFET转移特性曲线的影响; (c)带正电荷和带负电荷的固定陷阱电荷同时对GFET转移特性曲线的影响
Figure 8. TCAD simulation results: (a) Effect of a positively charged fixed trap charge on the transfer characteristic curve of GFET device; (b) effect of negatively charged fixed trap charge on the transfer characteristic curve of GFET device; (c) the effect of both positively charged and negatively charged fixed trap charges on the transfer characteristic curve of GFET devices.
表 1 电应力实验测试条件
Table 1. Electrical stress test conditions.
偏置电压条件 电应力测试时间点 转移特性曲线测试条件 栅极电应力(VG = –10 V, VD = 0 V, VS = 0 V) 0 s, 100 s, 300 s, 500 s, 1000 s VG 从–5 V扫到5 V, VD 为20 mV, VS 接地 漏极电应力 (VG = 0 V, VD = –10 V, VS = 0 V) 栅极电压与漏极电压同时施加的电应力(VD = –10 V, VD = –10 V, VS = 0 V) 
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