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Oxide indium gallium zinc thin film transistor (IGZO TFT) is a promising candidate for mass production of next-generation flat panel display technology with high performance. This is due to many merits of IGZO TFTs, such as high mobility, excellent uniformity over large area, and low cost. In recent years, IGZO TFTs with dual gate structure have attracted enormous attention. Compared with the conventional single gate IGZO TFTs, the dual gate IGZO TFTs have many advantages including increased driving ability, reduced leakage current, and improved reliability for both negative biasing stressing and positive biasing stressing. Although the measurement results of fabricated circuit samples have proven that dual gate IGZO TFTs are beneficial for the integration of digital circuit and active matrix light emitting display with in-array or external compensation schematics, there has been no proper analytic model for dual gate IGZO TFTs to date. As the analytic model is crucial to circuit simulations, there are great difficulties in circuit designs by using dual gate IGZO TFTs. Although there are some similarities between the operating principal of the dual gate IGZO TFTs and that of the dual gate silicon-on-insulator devices, the complexity of conducting mechanism of IGZO TFTs is increased due to the existence of sub-gap density of states (DOS) in the IGZO thin film. In this paper, an analytical channel potential model for IGZO TFT with synchronized symmetric dual gate structure is proposed. Gaussian method and Lambert function are used for solving the Poisson equation. The DOS of IGZO thin film is included in the proposed model. Analytical expressions for the surface potential (S) and central potential (0) of the IGZO film are derived in detail. And the proposed channel potential model is valid for both sub-threshold and above-threshold region of IGZO TFTs. The influences of geometry of dual-gate IGZO TFT, including thickness values of gate oxide layer and IGZO layer, on the device performance are thoroughly discussed. It is found that in the case of small gate-to-source voltage (VGS), as the conducting of IGZO layer is weak, both S and 0 increase linearly with the increase of VGS due to the increase of voltage division between the oxide and IGZO layer. However, the increase of S and 0 starts to saturate once VGS is larger than threshold voltage due to the shielding of electrical field by the induced electron layer of IGZO surface. With the evolution of VGS, the calculated results of S and 0 by using the proposed dual gate IGZO TFT model are in good agreement with the numerical results by technology computer aided design simulation method. Therefore, the proposed model is promising for new IGZO TFT electronics design automation tool development.
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Keywords:
- dual-gate thin film transistor /
- InGaZnO /
- channel potential /
- analytic model
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[22] Hoorfar A, Hassani M 2008 J. Inequalities Pure Appl. Math. 9 51
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[1] Kim Y, Kim Y, Lee H 2014 J. Dis. Technol. 10 80
[2] Zheng Z, Jiang J, Guo J, Sun J, Yang J 2016 Organic Electron. 33 311
[3] Liu F, Qian C, Sun J, Liu P, Huang Y, Gao Y, Yang J 2016 Appl. Phys. A 122 311
[4] Han D D, Chen Z F, Cong Y Y, Yu W, Zhang X, Wang Y 2016 IEEE Trans. Electron Dev. 63 3360
[5] Cai J, Han D D, Geng Y F, Wang W, Wang L L, Zhang S D, Wang Y 2013 IEEE Trans. Electron Dev. 60 2432
[6] Jeon C, Mativenga M, Geng D, Jang J 2016 SID Symposium (San Francisco: Wiley) 47 65
[7] Smith J T, Shah S S, Goryll M, Stowell J R, Allee D R 2014 IEEE Sensors J. 14 937
[8] Tai Y H, Chou L S, Chiu H L, Chen B C 2012 IEEE Electron Dev. Lett. 33 393
[9] Kaneyasu M, Toyotaka K, Shishido H, Isa T, Eguchi S, Miyake H, Hirakata Y, Yamazaki S, Dobashi M, Fujiwara C 2015 J. Soc. Inform. Dis. 46 857
[10] Baek G, Bie L, Abe K, Kumomi H, Kanicki J 2014 IEEE Trans. Electron Dev. 61 1109
[11] Hong S, Lee S, Mativenga M, Jang J 2014 IEEE Electron Dev. Lett. 35 93
[12] He X, Wang L Y, Xiao X, Deng W, Zhang L T, Chan M S, Zhang S D 2014 IEEE Electron Dev. Lett. 35 927
[13] Chang K J, Chen W T, Chang W C, Chen W P, Nien C C, Shih T H, Lu H H, Lin Y 2015 SID Symposium (San Jose: Wiley) 46 1203
[14] Baudrand H, Ahmed A A 1984 IEEE Electron. Lett. 20 33
[15] Young K K 1989 IEEE Trans. Electron Dev. 36 399
[16] Yuan T 2000 IEEE Electron Dev. Lett. 21 245
[17] Ortiz-Conde A, Garca-Snchez F J, Malobabic S 2005 IEEE Trans. Electron Dev. 52 1669
[18] Wang C C, Hu Z J, He X, Liao C W, Zhang S D 2016 IEEE Trans. Electron Dev. 63 3800
[19] Krner W, Urban D F, Elssser C 2013 J. Appl. Phys. 114 163704
[20] Torricelli F, ONeill K, Gelinck G H, Myny K, Genoe J, Cantatore E 2012 IEEE Trans. Electron Dev. 59 1520
[21] Alvarado J, Iiguez B, Estrada M, Flandre D, Cerdeira A 2010 Int. J. Number. Model. Electron. Netw. Dev. Fields 23 88
[22] Hoorfar A, Hassani M 2008 J. Inequalities Pure Appl. Math. 9 51
[23] Enz C C, Krummenacher F, Vittoz E A 1995 Analog Integr. Circuits Process. 8 83
[24] Chatterjee A, Machala C F, Yang P 1995 IEEE Trans. Computer-Aided Design Integr. Syst. 14 1193
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