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Monolayer molybdenum disulfide (MoS2) is an emerging two-dimensional (2D) semiconductor material.The MoS2 film has a natural atomic-level thickness, excellent optoelectronic and mechanical properties, and it also has the potential applications in very large-scale integration technology in the future. In this article we summarize the research progress made by our group in the studying of monolayer MoS2 films in the past few years. The controlled growth of large-size MoS2 single crystals is achieved by oxygen-assisted chemical vapor deposition method. By a unique facile multisource CVD growth method, the highly oriented and large domain size ML MoS2 films are epitaxially grown on a 4-inch wafer scale. Almost only 0° and 60° oriented domains are present in films, and the average size of MoS2 grains ranges from 100 μm to 180 μm . The samples exhibit their best optical and electrical quality ever obtained, as evidenced from their wafer-scale homogeneity, nearly perfect lattice structure, average room-temperature device mobility of ~70 cm2·V–1·s–1 and high on/off ratio of ~109 on SiO2 substrates. By adjusting the oxygen doping concentration in the MoS2 film through using an effective CVD technique, electrical and optical properties can be well modified, thereby greatly improving the carrier mobilities and controllable n-type electronic doping effects resulting from optimized oxygen doping levels of MoS2–xOx . In terms of MoS2 thin film devices and applications, the 4-inch wafer-scale high-quality MoS2 monolayers are used to fabricate the transparent MoS2-based transistors and logic circuits on flexible substrates. This large-area flexible FET device shows excellent electrical performance with a high device density (1,518 transistors per cm2) and yield (97%), and exhibits a high on/off ratio (1010), current density (~35 μA·μm–1), mobility (~55 cm2·V–1·s–1) and flexibility. Based on the vertically integrated multilayer device via a layer-by-layer stacking process, an individual layer of all-2D multifunctional FET is successfully achieved with nearly multiplied on-current density, equivalent device mobility, and persevered on/off ratio and subthreshold swing (SS) of the individual layer, the combined performance of the device is fully utilized, and the integration of “sensing-storing-computing” is realized. A two-terminal floating-gate memory (2TFGM) based artificial synapse built from all-2D van der Waals materials is prepared, the 2TFGM synaptic device exhibits excellent linear and symmetric weight update characteristics with high reliability and tunability. A large number of states of up to ≈3000, high switching speed of 40 ns and low energy consumption of 18 fJ for a single pulse are demonstrated experimentally. The introduction of structural domain boundaries in the basal plane of monolayer MoS2 can greatly enhance its hydrogen evolution reaction performance by serving as active sites. The progress we have made in the preparation of monolayer MoS2 films and the research on device characteristics is of guiding significance for the basic and application research of MoS2, and also is universal and instructive for other 2D transition metal dichalcogenides.
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Keywords:
- monolayer molybdenum disulfide /
- chemical vapor deposition /
- growth control /
- field-effect transistors.
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图 2 4 in蓝宝石晶圆上的单层MoS2的生长[16] (a) 多源CVD设备结构图[16]; (b) 被单层MoS2薄膜均匀覆盖的4 in蓝宝石晶圆照片[16]; (c)—(e) 流速为10 sccm的氧气环境中, 在蓝宝石衬底上分别生长20, 40和60 min的MoS2的光学图像, 其中图(d)右上角的刮痕是故意为之[16]
Figure 2. Growth of monolayer MoS2 on 4-in wafers[16]: (a) Schematic diagram of the multisource CVD setup[16]; (b) photograph of a 4-in sapphire wafer uniformly covered by monolayer MoS2 film[16]; (c)–(e) optical images of MoS2 grown on sapphire for different times with an O2 flow rate of ~10 sccm[16]. The top right corner in Figure (d) is an intentional scratch.
图 3 单层MoS2薄膜的结构表征[16] (a) 单层MoS2薄膜的AFM图像[16]; (b) 右上角带有人为划痕的MoS2薄膜荧光显微图像[16]; (c) 单层MoS2薄膜晶界位置的STEM图像[16]; (d) 图(c)样品紫色方框区域的STEM图像[16]; (e) 晶粒内部的STEM 图像; (f) 单层MoS2薄膜的SAED图像[16]
Figure 3. Structural characterizations of monolayer MoS2 film[16]: (a) AFM images of monolayer MoS2 films (the step structure is from the underlying sapphire surface) [16]; (b) fluorescence microscope image of the as-grown film with an intentional scratch on the upper right corner[16]; (c) typical STEM images of the MoS2 domain boundary[16]; (d) zoomed-in image of the rectangular area in Figure (c) [16]; (e) typical STEM images within a grain[16]; (f) SAED pattern of monolayer film[16].
图 4 生长的单层MoS2薄膜输运性质和逻辑门功能的表征[16] (a), (b) 生长的单层MoS2样品做成的FET的典型的转移特性曲线和输出特性曲线[16]; (c), (d) 随机选取的100个FET器件的开关比和迁移率测量统计[16]; (e) 本篇文章生长的MoS2样品在室温下的电学性能与其他工作的比较[16]; (f) 用生长的MoS2样品制作的逆变器的电压转移特性曲线(左轴)及源电压相应曲线[16]; (g)—(i) 与非门, 或非门, 与门逻辑器件的输出特性曲线[16]
Figure 4. Transport properties and logic gates of as-grown monolayer MoS2 films[16]: (a), (b) Output/transfer curves of a typical FET[16]. The on/off ratio (c) and mobility (d) of 100 random MoS2-FETs[16]; (e) comparison of MoS2 electrical performance at room temperature[16]; (f) voltage transfer characteristic of an inverter (left axis) and the corresponding voltage gain of the transfer curve (right axis) [16]; (g)–(i) output characteristics of NAND (g) NOR (h), and AND (i) gates[16].
图 5 氧气在不同生长阶段对晶畴尺寸的影响表征[22] (a) 当氧气流量为2 sccm时, 生长的单晶MoS2晶畴尺寸随生长时间的变化关系, 图中的红线和蓝线是拟合曲线[22]; (b) 生长过程中的刻蚀速率, 生长速率和时间的依赖关系, 蓝色的I 区域和红色的II 区域代表生长过程分别由生长主导和刻蚀主导[22]
Figure 5. Effect of oxygen on the domain size at various growth durations [22]: (a) Evolution of the size of single-crystal MoS2 domains as a function of the growth duration[22]; (b) dependence of pure growth rate and etching rate of MoS2 domains on the growth duration, the blue I and red II regions represent dominant growth and etching during the growth process, respectively[22].
图 6 (a) 保持其他生长条件不变, 在450—580 °C区间内改变MoO3温区的温度所得到的不同形状的MoS2晶畴的AFM图像(比例尺是1 μm)[38] (b) Mo锯齿边的生长速度与MoS2晶畴形状变化之间的对应关系[38]
Figure 6. (a) AFM images of MoS2 domains grown under the condition that the temperature of MoO3 changed from 450 to 580°C[38]; (b) the corresponding relationship between the shape change of MoS2 domains and the change of VMo[38]. Scale bar for (a) is 1 μm.
图 7 单层MoS2–xOx薄膜的生长[24] (a) 用于生长MoS2–xOx薄膜的三温区CVD系统的结构示意图[24]; (b) 生长 MoS2–xOx薄膜的相图以及设计的反应路线设计图[24]; (c)—(g) 通过增加O2流量(4—25 sccm)和降低衬底处的生长温度(930—880 ℃)来增加氧掺杂程度近而生长出不同形貌的三角形状的MoS2–xOx的光学图像, 其中图(e)左下角为MoS2–xOx的晶界的AFM图(比例尺是1 μm)[24]; (h) 通过控制生长过程中的O2流量实现异质结生长的光学图像[24]
Figure 7. The growth of monolayer MoS2–xOx films[24]: (a) Schematic set up of a three-temperature zone CVD system for synthesis monolayer MoS2–xOx films[24]; (b) the phase diagram and designed reaction routes for synthesizing MoS2-xOx[24]; (c)–(g) optical images of the synthesized MoS2-xOx triangles with increasing doping levels by varying the oxygen carrier gas flow-rate (FO2) from 4 to 25 sccm and growth temperature (TG) from 930 to 800 ℃[24]. Inset in Figure (e) is the AFM image across the boundary of MoS2–xOx triangle. Scale bar, 1 μm. (h) The controllable growth of MoS2–xOx heterostructures with FO2 of 20 sccm/6 sccm/10 sccm/6 sccm at 800 ℃[24].
图 8 MoS2–xOx样品的光学性质表征[24] (a) 在O2流量为6 sccm的条件下生长的MoS2–xOx样品的X射线光发射光谱[24]; (b), (c) 为不同氧掺杂程度的MoS2–xOx样品的Raman图和PL谱图[24]; (d)—(f) 在O2流量分别为6 , 10 sccm 以及 20 sccm/6 sccm/10 sccm/6 sccm的条件下生长的MoS2–xOx样品的荧光Mapping图[24]
Figure 8. The optical properties characterizations of MoS2–xOx [24]: (a) XPS spectra of MoS2–xOx synthesized with FO2= 6 sccm[24]; (b), (c) Raman and PL spectra of MoS2–xOx with increased oxygen doping levels[24]; (d)–(f) PL mapping of as-grown MoS2–xOx samples synthesized with FO2 of 4 (d), 10 sccm (e) and 20 sccm/6 sccm/10 sccm/6 sccm (f) [24].
图 9 在PET柔性基底上的MoS2晶体管结构示意图和柔型晶体管阵列的相关组成部分展示图[2] (a) 带有集成电路的柔性晶体管阵列的图示, 左插图: 通过外延技术生长的4 in单层MoS2晶圆[2]; (b) 在4 in蓝宝石衬底上生长了20 min的MoS2晶畴的光学图像, 其中三角形MoS2晶畴的边长约为20 μm[2]; (c) 生长40 min的连续单层MoS2薄膜的光学图像[2]; (d) 生长的单层MoS2的HRTEM图像[2]; (e) 大规模柔性MoS2晶体管阵列的照片(器件密度为1518 /cm2, 完全适合人类手腕)[2]; (f) 柔性MoS2晶体管阵列的照片, 显示其出色的光学透明度[2]; (g) 柔性衬底上的多种多级集成电路的照片, 包括逆变器, NOR门, NAND门, SRAM, AND门和五级环形振荡器[2]
Figure 9. Schematic and fabricated MoS2 transistor devices on flexible substrates of PET[2]: (a) Illustration of flexible transistor arrays with integrated circuits. Left inset: the 4-inch monolayer MoS2 wafer grown by epitaxy techniques. Right inset: the specific structure of the flexible MoS2-FETs[2]; (b) optical image of MoS2 domains grown on a 4-inch sapphire substrate for 20 min. The side length of the triangular MoS2 domain is ~20 μm[2]; (c) optical image of a continuous monolayer MoS2 film grown for 40 min[2]; (d) HRTEM image of the as-grown monolayer MoS2[2]; (e) photograph of very large-scale flexible MoS2 transistor arrays with a device density of 1518 /cm2, completely fitted to a human wrist. Inset: magnified image of FET arrays[2]; (f) photograph of the flexible MoS2 transistor arrays, showing their outstanding optical transparency[2]; (g) photograph of various integrated multistage circuits on flexible substrate, including inverters, NOR gates, NAND gates, SRAMs, AND gates and five-stage ring oscillators[2].
图 10 MoS2晶体管的电学性能表征[2] (a) 具有不同金属触点和电介质层的MoS2-FETs的转移特性曲线[2]; (b) Ti/Au和Au/Ti/Au电极的接触电阻的转移长度法(TLM)测量[2]; (c) 在不同温度下测量的Au/Ti/Au接触器件的转移曲线, 其中s是片状导电率, 左上方插图为不同栅压下的Arrhenius图[2]; (d) 有Au/Ti/Au接触的单层MoS2晶体管的SBH的栅压依赖关系曲线[2]; (e) 通道宽度和长度分别为30 μm和6 μm的器件的输出特性曲线[2]; (f) 不同偏置电压下相应的转移特性曲线[2]; (g) 100个晶体管阵列中97个柔性MoS2-FETs在Vsd=3 V时的转移特性曲线[2]; (h) 100个柔性晶体管的迁移率统计[2]; (i) 其他文献中报道的各种大面积柔性晶体管的开关比和迁移率与本器件的数据比较[2]
Figure 10. Performance characterization of the MoS2 transistors[2]: (a) Isd-Vg curves of MoS2-FET s with different metal contacts and dielectric layers[2]; (b) transfer-length-method (TLM) measurements of the contact resistance from the Ti/ Au and Au/Ti/ Au electrodes[2]; (c) transfer curves of Au/Ti/ Au contacted devices measured at various temperatures, where “s” is sheet conductivity[2]. Inset: Arrhenius plot at different Vg. (d) Vg dependence of the SBH for monolayer MoS2 transistors with Au/Ti/ Au contacts[2]; (e) Isd–Vsd output characteristics of a device with channel width and length of 30 μm and 6 μm, respectively[2]; (f) corresponding Isd-Vg transfer characteristics at different bias voltages[2]; (g) transfer curves at Vsd = 3 V for 97 flexible MoS2-FETs in the 100-transistor array. Inset: on/ off ratio map for each transistor location[2]. (h) Statistics of mobility from 100 flexible transistors[2]; (i) summary of the on/ off ratio and mobility for various large-area flexible transistors reported in the literature[2].
图 11 应力作用下的柔型器件的电学性能表征[2] (a) 柔性MoS2晶体管阵列在弯曲状态下的应变分布示意图[2]; (b) 单层MoS2在不同拉伸应变下的PL光谱[2]; (c) 柔性MoS2晶体管(L/W=3:1)在不同应变下的转移特性曲线[2]; (d) 随机挑选的柔性器件的沟道电流与应变之间的关系[2]; (e) 6个随机挑选的器件的载流子迁移率与应变之间的关系[2]; (f) 经受103次弯曲和释放循环测试的器件的通断率和电荷载流子流动性(在1%的应变下测量)其中插图为1%应变下的柔性器件的照片[2]
Figure 11. Electrical performance of flexible devices under strain[2]: (a) Schematic of the strain distribution of flexible MoS2 transistor arrays under bending[2]; (b) PL spectra of monolayer MoS2 under different tensile strains[2]; (c) Isd-Vg transfer curves of flexible MoS2 transistors (L/W = 3:1) at different strains[2]; (d) on and off currents of five randomly picked devices versus strain[2]; (e) the dependence of charge-carrier mobility on strain[2]; (f) on/ off ratio and charge-carrier mobility of a device subjected to 103 cycled tests of bending and releasing. Data were measured at 1% strain. Inset: photograph of flexible devices at 1% strain[2].
图 12 基于MoS2的柔性逻辑门和振荡器[2] (a) 柔性基底上不同MoS2集成器件的照片[2]; (b). 逆变器在不同弯曲状态下的输出电压与输入电压的关系[2]; (c), (d) 柔性NOR (c)和NAND (d)门在Vdd = 2 V时, 在器件弯曲前后的输出特性[2]; (e), (f) 灵活的SRAM(e)和AND(f)门在Vdd = 2 V时的输出特性[2]; (g) 五级环形振荡器在Vdd = 15 V时的输出波形[2]; (h) 输出频率是电源电压Vdd的函数, 其中误差条代表一个标准差[2]
Figure 12. MoS2-based flexible logic gates and oscillators[2]: (a) Photographs of different MoS2 integrated devices on flexible substrates[2]; (b) output voltage of an inverter as a function of input voltage when under different bending states. Inset: voltage gain of the inverter under an input of 4 V[2]. (c), (d) Output characteristics of flexible NOR (c) and NAND (d) gates before and after bending at Vdd = 2 V. Logic ‘0’ and ‘1’ mean 0 and 5 V, respectively, for these and all the following logic devices[2]. (e), (f) Output characteristics of flexible SRAM (e) and AND (f) gates at Vdd = 2 V[2]; (g) output waveform of a five-stage ring oscillator at Vdd = 15 V[2]; (h) output frequency as a function of supply voltage Vdd. Error bars represent one standard deviation[2].
图 13 在典型的底栅结构(SG)和双栅结构(DG)下的全二维场效应晶体管的器件结构和性能图[65] (a) 全二维器件的示意图截面图, 其中FLG, MoS2和h-BN分别作为接触/栅电极、通道和门电介质层[65]; (b) 具有SG和DG结构的全二维场效应晶体管的光学显微镜图像[65]; (c)—(f) 具有相同沟道(L = 3 μm, W = 10 μm)的SG((c), (d))和DG((e), (f))的FET的典型输出和转移曲线, 其中图(c)中的插图是在100 mV以内的小偏压下的输出特性曲线[65]; (g) 绝缘机制下的SBH特性是Vg的函数[65]; (h) SG和DG器件的Rc-Vg图[65]
Figure 13. Device structures and performances of all-2D FETs under both SG and DG geometries[65]: (a) Schematic cross section view of an all-2D device in which FLG, MoS2 and h-BN serve as contact/gate electrodes, channel, and gate dielectric layers, respectively[65]. (b) Optical microscope images of all-2D FETs with SG and DG. Bottom and top FLG gate is outlined by black dashed line. (c)–(f) Typical output and transfer curves of SG ((c), (d)) and DG ((e)–(f)) FET with the same channel (L= 3 μm, W= 10 μm). Insets in Figure (c) and Figure (e) are output characteristics at a small bias within 100 mV[65]. (g) SBH characterizations in insulating regime as a function of Vg. Insets are the cryogenic electrical transport curves of SG and DG FETs. MIT behavior could be observed from the DG device[65]. (h) Rc-Vg plots for both SG and DG devices, fitting from transfer length method[65].
图 14 通过逐层范德华力组装实现垂直集成的多层FET[65] (a) 由三层FET组成的器件结构的截面图[65]; (b) 垂直集成的从1到3层的FET的光学显微镜图像(堆栈内有垂直互联)[65]; (c), (d) 垂直集成1—3层器件的输出曲线(Vg = 12 V)和转移曲线(Vds = 1 V), 在单个FET中, 通道长度/宽度为3 μm/10 μm, 所有h-BN厚度约为30 nm[65]
Figure 14. Vertically integrated multilayer FETs through layer-by-layer vdW assembly[65]: (a) Schematic cross section view of the device structure consisting of 3 L FETs[65]; (b) optical microscope images of vertical integrated 1L to 3L FETs with vertical interconnects inside the stack. Scale bar: 20 μm[65]; (c), (d) output curves (at Vg = 12 V) and transfer curves (at Vds = 1 V) of vertical integrated 1L–3L devices. In an individual FET, channel length/width is 3 μm/10 μm, all h-BN thickness is around 30 nm[65].
图 15 (a)—(c) 范德瓦耳斯机制堆叠的多层的器件示意图 (a) 存储器(M1-M3, 第一层); (b). 逻辑(L1-L3, 第二层); (c) 传感器(S1-S3, 第三层)功能[65]; (d) 存储器件的典型I-V开关滞后[65]; (e) 反相器的输出电压Vout是输入电压Vin的函数, 漏极到漏极的电压Vdd在1到10 V之间变化(反相器是由第二器件层的器件L1-L2互联构成), 内页是原理图和最大增益值, 在Vdd=10 V时接近300[65]; (f) 逻辑NAND门在四个典型输入状态下的输出电压, Vdd=1.5 V(NAND门由第二层的器件L1-L2-L3互联实现)[65]; (g) 光学传感器在黑暗和蓝光环境下的静态光反应(光功率Pblue light=30 mW·cm-2), 偏压为1 V[65]; (h) 光学传感器在不同栅极电压下的动态光反应, 偏压为1 V[65]; (i) 传感器和存储器功能层之间的协同工作, 红色虚线所勾勒的存储器件(M3)的存储器件的阻态RS随着光学传感器(S1)的信号逐渐改变[65]
Figure 15. Vertically integrated multilayer functional devices: (a)–(c) Schematic illustration of vdW-stacking multiple layers with (a) memory (M1-M3, 1st layer), (b) logic (L1-L3, 2nd layer), and (c) sensor (S1-S3, 3rd layer) functions[65]. (d) Typical I-V switching hysteresis of a memory device[65]; (e) output voltage Vout of the inverter as a function of input voltage Vin with drain-to-drain voltage Vdd varying from 1 to 10 V (inverter is constructed by interconnecting devices L1-L2 in 2nd device layer). Insets are the schematic and the maximum gain value which approaches to 300 at Vdd= 10 V[65]. (f) Output voltage of the logic NAND gate at four typical input states with Vdd= 1.5 V (NAND gate is realized by interconnecting devices L1-L2-L3 in 2 nd layer) [65]. (g) Static photo response of the optical sensor under both dark and blue light environments (light power Pblue light = 30 mW·cm–2). Bias is 1 V. Inset shows the specific detectivity of the photodetector[65]. (h) Dynamic photo response of the optical sensor at different gate voltages with 1 V-bias reading. Light is turned on (blue shadow) for 5 s then turned off for 5 s[65]. (i) The cooperative working between sensor and memory functional layers. The RS of memory device (M3), outlined by the red dash line, is gradually changed with the signal from optical sensor (S1) [65].
图 16 全二维两端浮动门存储器(2TFGM)的器件结构和存储器特性[72] (a) 以单层MoS2为通道, 薄h-BN为隧道层, FLG为接触电极和浮动门的全2D材料2TFGM的示意图[72]; (b) 通道长/宽为3 μm/10 μm, h-BN的不同厚度为7—15 nm的FGM的典型半对数尺度I-V开关磁滞环, 虚线箭头表示扫频方向[72]; (c) 漏极/h-BN/FG在i编程和ii擦除过程中的带状图, 红色虚线箭头表示电子的隧道方向[72]; (d) 在300到500 K的高温下, 经过编程和擦除过程, 带有10 nm厚的h-BN的2TFGM的保留时间超过104 s (Vread = 1 V)[72]; (e) 经过105次开关操作的耐久性测试, 显示开/关比率没有恶化, 编程和擦除过程由±18 V进行, 脉冲宽度为100 ms, 读取电压为1 V[72]; (f) 器件开关速度测量, 在100和40 ns的短脉冲宽度(±23 V)下, 该器件仍然显示出稳定的电阻开关, 表明我们的器件具有很高的开关速度. 插图显示了宽度为100 ns/40 ns, 振幅为+23 V的电压脉冲[72]; (g) 制造的4×4的2 TFGM阵列的光学图像[72]; (h) 4×4的2TFGM阵列的电导状态的黑白“N07”图案的地图((i)—(iii))是通过操作2TFGM器件阵列来存储的[72]
Figure 16. Device structures and memory characteristics of all-2D two terminal floating-gate memory (2TFGM)[72]: (a) Schematic of the all-2D materials 2TFGM with monolayer MoS2 as the channel, thin h-BN as the tunneling layer, and FLG as the contact electrodes and floating gate[72]. (b) Typical semi-log scale I-V switching hysteresis loops of the FGMs with channel length/width of 3 µm/10 µm, and different thicknesses of h-BN from 7 to 15 nm. The sweeping directions are indicated by the dashed arrows. Insets are the corresponding optical images of 2TFGMs with scale bars of 10 µm[72]. (c) Band diagrams of the drain/h-BN/FG at the (i) programming and (ii) erasing processes. The red dashed line arrows indicate the tunneling direction of electrons[72]. (d) Over 104s retention time of 2TFGM with 10 nm-thick h-BN after the programming and erasing processes at elevated temperatures from 300 to 500 K (Vread=1 V). Two explicit resistance states could be preserved at 400 K[72]. (e) Endurance test with 105 cycles of switching operations showing no deterioration on the on/off ratio. Programming and erasing processes are carried out by ±18 V with a pulse width of 100 ms and a reading voltage of 1 V[72]. (f) Device switching speed measurements. The device still shows stable resistance switching under short pulse widths of 100 and 40 ns (±23 V), indicating the high speed of our device. Inset shows the voltage pulse with width of 100 ns /40 ns and amplitude of +23 V[72]. (g) Optical image of the fabricated 4 × 4 2TFGM array[72]. (h) The color map of conductance states of the 4 × 4 2TFGM array. The map of “N07” patterns ((i)–(iii)) are stored by operating the 2TFGM devices array[72].
图 17 人工突触行为的特征[72] (a) 生物神经元的示意图, 包括体细胞、轴突、树突以及突触, 即两个相邻神经元之间的连接点[72]; (b) 突触后电流与脉冲数的关系, 显示了2TFGM装置所模拟的长期电位和抑制特性, 在2TFGM人工突触中, 通过一系列±15 V(40 ns)的编程/消除脉冲, 对3000个不同的状态进行了编程[72]; (c), (d) 示波器捕捉到的P/D过程中的瞬态反应[72]; (e), (f) 图(c)和图(d)中几个周期的放大图, 模拟兴奋性突触后电流(EPSC)和抑制性突触后电流(IPSC)[72]
Figure 17. Characterizations of artificial synaptic behaviors[72]: (a) Schematic illustration of biological neurons, consisting of a soma, an axon and dendrites, and synapses, which are the conjunctions between two neighboring neurons. The enlarged area illustrates the synaptic transmission of neurotransmitters between the axon terminal of pre-synaptic neuron and the dendrite of post-synaptic neuron[72]. (b) Post-synaptic current versus pulse number, demonstrating long-term potentiation and depression characteristics emulated by our 2TFGM device. 3000 distinct states are programmed in our 2TFGM artificial synapse through a series program/erase pulses of ±15 V (40 ns)[72]. (c), (d) The transient responses during the P/D process captured by oscilloscope[72]; (e), (f) The enlarged view of several cycles in Figure (c) and Figure (d), mimicking excitatory postsynaptic current (EPSC) and inhibitory postsynaptic current (IPSC) [72].
图 18 对神经形态计算的线性和对称权重更新的追求[72] (a), (b) 在P/D过程中, 器件电导率的变化是脉冲宽度(a)和振幅(b)的函数[72]; (c) P/D过程中的线性、开/关比和状态数通过电压脉冲幅值(从±10到±13 V, 100 ms)调节的关系图[72]; (d) 对图(c)中不同P/D曲线的权重更新进行非线分析, 其中橙色虚线代表权重更新的理想线性度和对称性[72]; (e) 2 TFGM人工突触的循环P/D操作, 使用一系列振幅为±12 V、宽度为100 ms的脉冲对至少50个状态进行编程, 显示了突触权重更新的良好可重复性、线性和对称性[72]; (f) 在不同的P/D过程下, 来自MNIST数据库的手写数字的图像分类准确性是训练历时的函数, 使用400个状态和Vds = ±10 V的P/D过程, 实现了97.7%的高识别准确率[72]; (g) 在图(f) 中不同的P/D过程对应的20个训练周期后的错误率. 插图显示了模拟的神经网络结构, 这里用标准反向传播算法模拟了一个三层感知器(包括一个隐藏层)[72]
Figure 18. The pursuit for linear and symmetric weight update for neuromorphic computing[72]: (a), (b) The changes in the device conductance as a function of pulse width (a) and amplitude (b) during the P/D process[72]. (c) The linearity, on/off ratio, and number of states in the P/D process could be tuned by adjusting the amplitude of voltage pulses from ±10 to ±13 V (100 ms)[72]. (d) Nonlinearity analysis on the weight update of the different P/D curves in Figure (c). The orange dashed lines represent the ideal linearity and symmetry of weight update[72]. (e) Cycled P/D operations of the 2 TFGM artificial synapse. At least 50 states are programmed using a series of pulses with amplitude of ±12 V and width of 100 ms, demonstrating good reproducibility, linearity, and symmetry in the synaptic weight update[72]. (f) The image classification accuracy for hand-written digits from the MNIST database under different P/D processes as a function of the training epoch. A high recognition accuracy of 97.7% is achieved using the P/D process of 400 states and Vds=±10 V[72]. (g) The error rate after 20 training epochs corresponding to different P/D processes in Figure (f). Inset illustrates the simulated neural network structure. Here a three-layer perceptron (including one hidden layer) is simulated with the standard backpropagation algorithm[72].
图 19 (a) 分别是原始I型MoS2(无任何域界)、原始III型IMoS2(有2H-2H域界)、异相I型MoS2(有2H-1T相域界)和异相III型MoS2(有2H-2H和2H-1T域界)的偏振曲线[5]; (b) 图(a)中相应曲线的Tafel图[5]
Figure 19. (a) Polarization curves of the pristine type-I MoS2 (without any domain boundaries), pristine type-III MoS2(with 2H-2H domain boundaries), heterophase type-I MoS2(with 2H-1T-phase domain boundaries), and heterophase type-III MoS2(with both 2H-2H and 2H-1T domain boundaries), respectively[5]. (b) Tafel plots of the corresponding curves in Figure (a) [5].
图 20 (a) 同时具有高密度晶界和相界的MoS2催化剂的结构示意图[5]; (b) 原始II型样品、原始III型样品、由III型样品衍生的一系列具有不同相界密度的混相和Pt的极化曲线[5]; (c) 图(b)中对应曲线的Tafel图[5]; (d) 高密度晶界, 相界的MoS2催化剂在0.5-M H2SO4(红色曲线)和1-M KOH(紫色曲线)中的HER性能[5]; (e) 高密度晶界, 相界的MoS2催化剂在150 mV的静态过电位下200 h的时间依赖性电流密度曲线[5]; (f) 直径为4 in的多层MoS2催化剂在0.5-M H2SO4中催化HER活性的演示图, 其中插图蓝宝石基底上原始的原生晶圆级MoS2照片[5]
Figure 20. Multi-hierarchy monolayer MoS2 catalysts for HER[5]: (a) Schematic structure of the multi-hierarchy MoS2 catalysts with both high density of domain and phase boundaries[5]; (b) polarization curves for pristine type-II samples, pristine type-III samples, a series of heterophase type-III samples with different phase boundary densities and Pt[5]; (c) Tafel plots of the corresponding curves in Figure (b)[5]; (d) HER performance of a multi-hierarchy MoS2 catalyst in 0.5-M H2SO4 (red curve) and 1-M KOH (purple curve) [5]; (e) time-dependent current density curve for a multi-hierarchy MoS2 catalyst under static overpotential of 150 mV for 200 h[5]; (f) demonstration of the catalytic HER activity in 0.5-M H2SO4 from a multi-hierarchy MoS2 catalyst with a size of 4 inches in diameter. Inset: photograph of pristine as-grown wafer-scale MoS2 on sapphire substrate[5].
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