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By using the first-principles method based on density functional theory and non-equilibrium Green's function, the transport properties of 5-nm two-dimensional SiC field-effect transistors with asymmetric metal phase 1T-MoS2 sources and Pd drain electrodes are investigated. The influence mechanism of increasing the electrode layers of 1T-MoS2 and reducing the working electrical compression on the device performance is systematically analyzed. The Schottky barriers extracted from the zero bias and zero gate voltage transport spectra show that the valence band maximum of SiC in the channel regions of MFET, BFET and TFET are closer to the Fermi level after the source drain electrode has been balanced. Therefore, these three devices belong to P-type contact, and the height of the hole Schottky barrier increases with the increase of the number of 1T-MoS2 layers in the source electrode, which are 0.6, 0.76, and 0.88 eV, respectively. In addition, the increase of 1T-MoS2 layers will also lead to the increase of the density of states in the source electrode, thereby improving the transport coefficient at the band edge. The effects of the two on the transport capacity of the device are opposite, and there is a competitive relationship. The transfer characteristics of devices show that the wide band gap of SiC can significantly suppress the short channel effect, so that all devices can meet the requirements of Off-state. More importantly, the subthreshold swings of all devices at an operating voltage of 0.64 V are all close to the physical limit of 60 mV/dec. The ON-currents of MFET, BFET and TFET can reach 1553, 1601 and 1702 μA/μm under the more stringent IRDS HP standard, and the three performance parameters, i.e. intrinsic gate capacitance, power-delay product and delay time, can greatly exceed the standards in the international road map of equipment and systems (IRDS) for high-performance devices. In addition, the working voltage of MFET can be reduced to 0.52 V, and the corresponding power-delay product and delay time are as low as 0.086 FJ/μm and 0.038 ps, which are only 14% and 4% of the IRDS standard. The asymmetric source drain electrode design strategy proposed in this work not only solves the problems about low Onstate current and short channel effect restricting Off-state current of existing two-dimensional material Field-effect transistors, but also provides an important solution for developing ultra-low power nano electronic devices in the post Moore era.
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Keywords:
- two-dimensional material /
- first principles /
- field-effect transistor /
- transfer characteristic /
- short channel effect
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图 1 金属相1T-MoS2和Pd金属为非对称源漏电极的5 nm二维SiC场效应晶体管的结构图
Figure 1. Detailed structure of 5 nm FET based on two-dimensional SiC with metal 1T-MoS2 contact (source) and palladium contact (drain).
图 2 (a) MFET, (b) BFET和(c) TFET在零偏压和零栅极电压下的输运谱和投影局域态密度. 费米能级在能量标度中设置为零
Figure 2. Transmission spectra and the projected local density of states (LDOS) of (a) MFET, (b) BFET, and (c) TFET under zero-bias voltage and zero-gate voltage. The Fermi level is set to zero in the energy scale.
图 3 MFET, BFET和TFET的转移特性(a), 开态电流(b)和亚阈值摆幅(c)
Figure 3. Transfer characteristic (a), ON-current (b), and subthreshold swing (c) of MFET, BFET and TFET, respectively.
图 4 (a) MFET在0. 6 V, 0. 56 V, 0. 52 V, 0. 48 V和0. 44 V 工作电压VDD下的(a)转移特性, (b)开态电流和(c)亚阈值摆幅
Figure 4. (a) Transfer characteristic, (b) ON-current, and (c) subthreshold swing of MFET under VDD of 0.6 V, 0.56 V, 0.52 V, 0.48 V, and 0.44 V, respectively.
表 1 MFET, BFET和TFET的性能与IRDS的高性能设备要求的对比
Table 1. Performances of the MFET, BFET和TFET against the HP devices requirements of the IRDS.
Cg/
(fF·μm–1)PDP/
(fJ·μm–1)τ/
psIRDS标准 0.39 0.49 0.96 MFET (VDD = 0.64 V) 0.150 0.061 0.064 BFET (VDD = 0.64 V) 0.155 0.063 0.064 TFET (VDD = 0.64 V) 0.134 0.055 0.051 MFET (VDD = 0.60 V) 0.146 0.071 0.056 MFET (VDD = 0.56 V) 0.138 0.078 0.043 MFET (VDD = 0.52 V) 0.142 0.086 0.038 
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